This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
Sampling analog signals at billions of times per second requiresvery carefully designed mixed signal systems. Time interleaving orsynchronising multiple converters is a recognised system level issue.Here, we explore the inherent design challenges and provide usefulguidelines for interleaved analogue to digital converter (ADC) systemdesign. Analog input signal conditioning, clock design and layout, gainand phase matching are discussed. FPGA data handling and capturing isalso explored. Innovative new ADC integrated features for interleavingare introduced and measured FFT results are presented.
The ADC08xxxx gigasample family of ADCs can enable high performancedata acquisition systems at very low power – which is often thelimiting factor in such systems. When and why is it an advantage toincrease sampling frequency and how much sampling speed is required?There are several answers to this question. Essentially an ADC'ssampling speed directly determines the instantaneous bandwidth that canbe digitised in one sampling instant. The Nyquist and Shannon samplingtheorems state that the maximum available sampling bandwidth (BW) isequal to the half the sample frequency (FS):
BW = FS/2
A 3GSample/s ADC allows a 1.5GHz analogue bandwidth signal to beinstantaneously sampled. Doubling the sampling speed also doubles thesampling bandwidth to 3GHz. The converter front end of course must alsobe able to accommodate this bandwidth. The inherent increased samplingbandwidth gained by time interleaving is beneficial in manyapplications.
Software radio architectures, for example, can increase the numberof information channels ” and therefore the throughput ” that can behandled. Over-sampling a signal also allows progressive gain benefitsin the digital domain by means of digital filtering. Doubling theNyquist sampling rate gives a 3dB improvement in dynamic range. Everyfurther doubling of the sampling frequency provides an additional 3dBof dynamic range.
|Figure1. Time domain measured plots of 247.77 MHz signal sampled at 30 (top)and 8 (bottom) GSPS sample rates|
There are several other advantages gained by increasing samplefrequency. Increasing FS increases resolution in LIDAR systems, whichoperate on the principle of time of flight (TOF) measurements.
Digital oscilloscopes also require high FS to input frequencyratios, for acquiring fast analogue or digital signals. If the scopesampling frequency is too low, a square wave no longer looks like asquare wave. Figure 1 above illustrates the benefit of doubling sampling frequency in anoscilloscope front end.
The 6Gsample/s waveform is a much better representation of the trueanalogue input. Many other test instrumentation applications, such asmass spectrometry, depend on high over-sampling ratios for pulse shapemeasurements.
Time interleaving ADCs presents three difficult challenges;accurately aligning sampling clock phase, channel to channel analoguegain and offset matching, and output digital data synchronisation.Luckily, National Semiconductor's family of Gigasample converters haveseveral innovative integrated features specifically addressing thesechallenges.
Sampling clock phase adjustment
Generally a 2-channel interleaved converter architecture requires thatthe ADC input sampling clocks are time shifted by half a clock period.However the ADC083000 architecture uses on-chip interleaving andoperates with a clock frequency equal to half the sample rate, i.e.1.5GHz to achieve 3GSPS. Therefore for a 2-channel system employing twoADC083000's, the ADC input sampling clocks must be time shifted by onequarter of a clock period, or 90° with respect to each other. Thiscorresponds to 166.67ps for a 1.5GHz clock. This is presentedgraphically in Figure 2 below.
The second ADC, ADC 2 should be laid out such that its clock inputtrace is longer than ADC 1's. For FR04 PCB material, a signalpropagates at 20cm/ns, or 1cm in 50ps. The clock signal's “T” point canbe laid out to minimise the required on-chip tuning. For example if theclock trace to ADC 2 is 3cm longer than to ADC 1, this will result in a150ps phase shift. The challenge then is to accurately meet theadditional 16.67ps time shift.
|Figure2: A 90 degree phase shift results in four samples per input clock cycle|
The ADC083000 has an integrated adjustable clock phase featurethatallows the system designer to program a delay on the ADC input clock toshift the sample clock phase relative to another ADC. The clock phaseof the ADC can be adjusted manually through two internal registers overan SPI bus. The coarse adjust register has 4bit resolution and each LSBresults in approximately 70ps of clock adjust.
The fine adjust register has 9bit resolution, allowing 512 steps or110ps total adjustment. Therefore each LSB results in approximately0.2ps of clock adjustment. Coarse adjustment is useful when largeadjustments are required due to non optimal clock trace layout and if aboard designer wants to adjust for differences between adjacent channelconverter input clock to output data delay (tOD) in a non-interleaved,multi-channel data acquisition system.
The phase shift is only possible in one direction, increasing delay.The designer should determine which of two discrete ADCs is “ahead” andadjust its phase so that its sample edges are 90º between theother ADC's sample edges.Measuring phase alignment
Using available ADC evaluation software, in this case National'sWaveVision 4 software, the output spectrum of the ADC can be plotted inthe form of an FFT. Equations 1 and 2 can then be used to determine thetiming offset or shift between input clocks. Equation 1 above shows that thepower in the image spur at FS/2 ” FIN is proportional to the timingoffset between the two sampling clocks.
Re-arranging the formula, Equation2 below shows that the timing offset is 1.82ps ascalculated from the power in the image spur of -59.959dBc. 1.82ps isonly 0.273% of ADC clock period at 1.5GHz and since the image spur isnot the dominant SFDR spur, the system designer has reached therequired level of clock phase adjustment accuracy.
In a two-converter interleaved system, the error voltages generatedby channel gain mismatches result in image spurs that are located atFS/2 ” FIN and FS/4 +/- FIN. An 8bit converter has 28 or 256 codes.Assuming the converter full scale input range is 1V p-p, the LSB sizeis equal to 1V/256 = 3.9mV. We can then calculate that the requiredgain matching for half an LSB accuracy is 0.2%.
The input full-scale voltage or gain of the ADC083000 can beadjusted linearly and monotonically with a 9bit data value. Theadjustment range is ±20% of the nominal 700mVp-p differentialvalue. 0000 0000 0 gives 560mVp-p and 1111 1111 1 results in 840mVp-pas shown below:.
840mV ” 560mV =280mV
29 = 512 steps
280mV / 512 =546.88¼V
This degree of fine adjustment allows greater than 0.2% gainmatching as required above.
Offset mismatching between adjacent channels generates an errorvoltage that results in an offset spur, that is located at FS/2. Sincethe offset spur is located at the edge of the Nyquist band, designersof two-channel systems can typically plan their system frequency aroundit and focus their efforts on gain and phase matching.
However let us assume that the required offset matching is alsoquarter an LSB. The input offset of the ADC083000 can be adjustedlinearly and monotonically from a nominal zero offset to 45mV of offsetwith 9bit resolution. Thus, each code step provides 0.176mV of offset.Again this resolution allows a quarter LSB accuracy to be achieved.
Synchornization of digitaloutputs
The last remaining challenge is to synchronise the output data streamsfrom both ADCs. The system developer must be able to correlate theinput sampling points to the output data words from each ADC.
The ADC outputs cannot be successfully multiplexed together torealise the combined sampling speed and bandwidth unlesssynchronisation is achieved. In other words, meaningful data capture isnot possible if loss of output synchronisation occurs. NationalGigasample ADCs 'demux' the output data in order to reduce the digitaloutput data rate. The user has the option of 'demuxing' the data rateby 2 or 4, depending on the speed grade of the FPGA technology used.
The output capture clock (DCLK) is also divided by two, whichsimplifies data capture in an FPGA by increasing the equivalent datacapture window. Demuxing however introduces an additional considerationbecause there is now added uncertainty about the correspondence betweenthe input sampling clock and the DCLK output of each ADC.
To overcome this the ADC083000 has the capability to precisely resetits sampling clock input to DCLK output relationship as determined bythe user-supplied DCLK_RST pulse. This allows multiple ADCs in a systemto have their DCLK (and data) outputs transition at the same time withrespect to the shared input clock that they use for sampling, allowingsynchronisation between multiple ADCs to be achieved.
In the practical realisation of such a system, the designer mustalso take into consideration the error sources from other componentsused; e.g. amplifier output gain and offset errors, transformer phaseand gain mismatches, clock source skew and jitter. These error sourcesmust be quantified and accounted for.
To the majority of consumers, the electronics world isdominated bydigital signals, from telecommunications to multimedia. The truth,however, is it depends on analogue to create it.
Paul McCormack is Senior ApplicationsEngineer Data Conversion Division, Europe, Data Converters,