Target Compiler Technologies has announced enhancements and additions to its product line that enable IP subsystem design. Key among these additions is broad support for both multicore and multithreaded architectures, providing task-level parallelism delivered by multicore and multithreaded architectures. Increasing subsystem parallelism with such architectures keeps design teams on target with respect to needed improvements in performance and power efficiency.
MP Designer is a tool suite that helps engineers balance both software and hardware decisions for multicore subsystems. MP Designer allows engineers to quickly explore software parallelization and hardware architecture options to search for optimal solutions. It works directly off of sequential C code, generating parallel implementations and guaranteeing correctness. MP Designer includes an intuitive and integrated multicore debugger, simplifying software debug for complex, parallelized applications.
IP Designer tool suite for the design of application-specific processors (ASIPs) now provides modeling of multi-threaded architectures. Architectural solutions supported include preemptive multithreading schemes with infrequent context switching suited for low-power systems, as well as advanced barrel processors with interleaved multithreading.
A significant increase in scope in IP Designer’s modeling capability allows designers to model advanced communication and memory interfaces for their ASIPs. Typical examples include bus interfaces, memory banks, and cached memories. IP Designer automatically generates the hardware implementation of such interfaces, as well as a simulation model enabling virtual prototyping of the ASIP in its subsystem.
MP Designer and extensions to IP Designer are available today from Target Compiler Technologies . Visit Target Compiler at booth 2142 at 50th Design Automation Conference.