Technology for FPGAs and PLDs - Embedded.com

Technology for FPGAs and PLDs

A programming technology, called ispXP (for in-system programmableeXpanded Programmability), from Lattice Logic, provides non-volatilein-system programmability combined with reconfigurability via amicroprocessor sysCONFIG port.

The architecture, based on a set of homogeneousmulti-function-blocks that can implement a variety of functions basedon the user's application requirements, supports both logic andmemory on-chip with up to 300K system gates in a single device.

Functions of up to 136 inputs can be implemented in a single levelof logic for wide parallel logic processing.

The company has developed both FPGA and PLD architectures whichincoprate the technology.

The ispXPGA (in-system programmable eXpanded Programmable GateArray) family combines on-chip E2 memory with SRAM cells in anon-volatile architecture which allows infinite reconfiguration.

The ispXP devices in the ispXPGA family self-configure inmicroseconds at power-up ('instant on'), so they are available to anelectronic system during its power-up sequence.

The ispXPGA family covers 125Kgates to 1.2Mgates or 2K to 15Klogic elements. Gates are counted using the industry-standardapproach. Block RAM goes from 92K to 414K bits, while distributedRAM reaches from 30K to 246Kbits. The family has products from 160to 496 I/Os, including 4 to 20 sysHSI clock pairs.

The ispXPGA family provides a PFU (programmable function unit),hardware-accelerated arithmetic and muxing that enhance performance,distributed single-port, dual-port, FIFO, and shift-register memoryfor local scratchpad needs.

Wide-gating expansion is provided for operations with up to 20inputs and there are two flip-flops per look-up table to improveefficiency/speed of library elements, pipelining, andregister-retiming for boosting fMAX.

There are sysMEM embedded 4k-bit memory blocks, single-port,dual-port, and FIFO configurations and parity is provided with x9 andx18 support. The sysIO input/outputs give a choice of dozens of I/Otypes for single-ended and differential needs.

The sysHSI (high-speed interface) provides 850Mbit I/Os withSERDES and clock recovery for handling ultra-fast data streams. Theinitial ispXPGA device is the 1.2 million gate LFX1200.

The ispXPLD family also uses the ispXP technology that combinesthe traditional product-term based PLD benefit of 'instant-on',non-volatile programming together with real time, unlimitedreconfigurability found in SRAM-based FPGAs.

Lattice's development provides it with devices that combine thespeed, predictability and non-volatility of CPLDs together with thesystem-level features, density and reconfigurability of FPGAs.

The initial series of ispXPLD devices, the ispXPLD 5000MX family,will be available in 1.8, 2.5 and 3.3V power supply versions,designated the 5000MC, 5000MB and 5000MV series. The devices will beoffered in 256, 512, 768 and 1024 macrocell-equivalent densities with141 to 381 user I/O, corresponding to 75K to 300K system gates.

The first device is the ispXPLD 5512MX, packaged in a 484 finepitch BGA package.

Programmable sysIO interface capability provides flexible advancedI/O standard (GTL+, HSTL, SSTL, LVDS, etc.) support.

Advanced silicon technology, combined with proprietary circuitdesign techniques, provides standby power consumption as low as36mW/device for power-sensitive applications. Each device alsoincorporates Lattice's sysCLOCK PLL capability for high-performanceon-chip clock synthesis.

The homogeneous ispXPLD architecture consists of a number ofuniform multi-function blocks interconnected by a single-level, highspeed programmable global routing pool (GRP). The GRP also connectsthe MFBs to the I/O cells. Devices in the ispXPLD 5000MX familyintegrate from 8 to 32 MFBs into a single device. Each MFB within anispXPLD device can be programmed independently to implement 32macrocells of SuperWIDE logic, an 8kbit dual port RAM, a 16kbitSingle Port RAM or FIFO, or a 128 by 48 bit content addressablememory (CAM).

Dedicated FIFO control logic is included on-chip so programmableresources are not consumed providing these memory control functions.While the basic logic block configuration supports up to 68 logicinputs in a single level of logic, cascading MFBs allows the devicesto support functions of up to 136 inputs without incurring anadditional level of logic delay.

Each I/O pin on the devices can be configured to supporthigh-speed memory interfaces, advanced bus standards, orgeneral-purpose interfaces. General-purpose interface supportincludes LVTTL or LVCMOS (3.3, 2.5 or 1.8V). Four independent I/Obanks provide support for multiple interface voltages and standardson a single device.

Published in Embedded Systems (Europe) September 2002

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