This week instrumentation provider Tektronix, Inc., introduced version 2.0 of its Certus ASIC prototyping debug suite of software and RTL-based embedded instruments
According to Brad Quinton, chief architect for the embedded instrumentation group at Tektronix, Certus 2.0 fundamentally changes the ASIC prototyping flow by enabling full RTL-level visibility and making FPGA internal visibility a feature of the prototyping platform. This simulation-level visibility allows engineers to diagnose multiple defects in a day versus a week or more with existing tools.
“Because we are now delivering RTL-level visibility of up to a hundred thousand signals spanning the entire design, the debugging use case is comparable to RTL simulation,” he said.
”This enables the direct debugging of hardware and software on the ASIC prototype without going back to simulation, emulation or acceleration platforms, changing the economics of ASIC silicon-based verification.”
Quinton said that a major challenge today is that traditional FPGA debug tools are unable to support the requirements of the ASIC prototyping market, particularly as designs have become larger and span multiple FPGA devices.
“Add the increased complexity of hardware/software interactions and the high-speed operation of most prototypes, and FPGA debug has become a major bottleneck in the ASIC prototyping process,” he said. “Now, by pre-instrumenting up to one hundred thousand signals per FPGA device, designers gain comprehensive RTL-level signal visibility without time consuming synthesis and place and route cycles, allowing complex problems to be pinpointed and resolved quickly.”
Proactive debug strategy
Quinton said Certus 2.0 is designed to allow embedded hardware and chip designers to automatically instrument all the signals likely to be needed in each of the FPGAs in a multi-FPGA ASIC prototype with a small FPGA LUT impact.
“This enables a proactive debug and instrumentation strategy, eliminating the need to re-compile the FPGA to debug each new behavior, typically a painful eight to eighteen hour ordeal with traditional tools,” he said. ther key capabilities include:
* Automatic identification and instrumentation of RTL signals based on type and instance name including flip-flops, state machines, interfaces and enumerated types
* On-chip, at-speed capture and compression of many seconds of data without special external hardware or consuming FPGA I/O resources
* Advanced on-chip triggering bringing the power of logic analyzer trigger methods to embedded instrumentation
* Time-correlated capture results across clock domains and multiple FPGAs providing a system-wide view of the entire target design
Certus 2.0 works on any existing commercial or custom ASIC prototyping platform, and does not need special connectors, cables, or external hardware. In addition, Certus 2.0 does not limit the operating speed of the prototype platform.
Certus is the outgrowth of Tektronix’s embedded instrumentation strategy following the acquisition of Veridae Systems last year. It reflects, said Quinton, the growing importance of Electronic Design Automation (EDA) software in helping engineers solve difficult instrumentation and debug challenges.
The Certus 2.0 ASIC prototyping debug suite is available now and is priced at $19,500 U.S. MSRP for a one year term-based floating license.