Tektronix Inc. has enhanced its PCI Express 3.0 tool with physical layer transmitter (Tx) verification, debug, characterization and compliance testing using Tektronix DPO/DSA/MSO70000 series oscilloscopes.
The PCIe 3.0 architecture provides a high-performance I/O technology that includes a 128b/130b encoding scheme and a data rate of 8 GT/s, doubling the interconnect bandwidth over PCIe 2.0. Based on the same board material (FR4) and connectors as previous generations, PCIe 3.0 represents a far more difficult test challenge with smaller margins and new jitter measurements required to account for increased signal loss in the channel.
The Tektronix PCIe 3.0 solution (Option PCE3) builds on the success of PCIe Gen 1 and Gen 2 test solutions. Coupled with Serial Data Link Analysis (SDLA) software, it provides a complete solution for verifying transmitter and channel performance of PCIe 3.0 designs and provides support for both the PCIe 3 Base Specification and CEM Specification measurements.
The electrical testing support provided by the Option PCE3 solution complements the Tektronix TLA7SA16 and TLA7SA08 logic protocol analyzer modules, bus support software, and probes announced earlier this year that bring PCIe 3.0 logical and protocol testing support to the TLA7000 Series logic analyzer family.
Option PCE3 accelerates the analysis and validation of PCIe designs and provides the flexibility to check devices for precompliance or perform device characterization or debug in a single software package.
Serial Data Link Analysis software enables channel de-convolution, convolution and receiver equalization. DPOJET jitter and Eye-diagram analysis software provides jitter, eye-diagram and parametric testing. And the P7520 TriMode Differential Probe is available for validation and debug of chip-to-chip links, including common mode measurements.
Performance validation and stress testing of PCI Express 3.0 receiver designs will also be critical given the large speed increase in the standard. The BERTScope BSA85C provides stressed pattern testing with jitter and interference added to determine effective Bit Error Ratio from new receiver designs.
The BERTScope is complemented by the DPP125B which adds critical pre-emphasis to the stressed pattern, and the CR125A that recovers the embedded clock to allow for eye diagram analysis on the resulting signal. BERTScope provides a true Bit Error Ratio in addition to eye diagram analysis for complete debug of PCIe3.0 receivers.
These tools integrate with the TLA7SA16 and TLA7SA8 Logic Protocol Analyzer modules to provide complete visibility of PCIe 3.0 physical and logical layers. The combination of the two solutions allow for PCIe 3.0 digital debug and validation, analog validation, compliance testing, and device characterization.