LONDON In a effort to simplify Electronic System Level (ESL) adoption, Tenison Design Automation and SpiraTech have signed an OEM agreement and technology integration deal which will see Tenison integrate SpiraTech’s Cohesive Transactor technology with its VTOC product and resell the packaged product to its customers.
The integrated product will provide a turnkey solution for complete system level modeling (SLM) within ESL design platforms, including ARM RealView SoC Designer, CoWare ConvergenSC, and OSCI SystemC. The OEM package provides a seamless method to incorporate existing RTL designs as high performance transaction level models within ESL design environments.
Tenison’s (San Jose, CA) VTOC provides the technology to convert designs to fast SystemC models and SpiraTech’s (Manchester, England) Cohesive Transactors provide high performance bus transaction interfaces to those models. Users are able to connect third party bus transactional models, such as instruction set simulators to models with their existing RTL designs to provide a comprehensive, high performance system modeling solution.
Increasing chip complexity demands design flows that can scale and reduce development time and Tenison says functional system verification capacity is the bottleneck in developing these design flows. To achieve the required verification throughput, designs need to be modeled and mixed at multiple levels of abstraction — RTL, cycle callable and bus transactional.
Incorporating SpiraTech’s Cohesive Transactor technology, Tenison VTOC models derived from RTL will be available at bus transactional levels (often know as Programmers View and Programmers View with Time models), with an associated increase in performance. Customers should then be able to speed up functional verification of SoC’s — both hardware and software — with an automated process to link existing RTL to high-speed bus – transactional models.
Tenison is demonstrating the Tenison-SpiraTech integration within ARM RealView SoC Designer and releasing the results of the first transaction level modeling of a complete multi-core SoC design incorporating legacy RTL modeled using Tenison VTOC and SpiraTech Cohesive. VTOC has also been interfaced with the ARM RealView SoC Designer with MaxSim technology, for incorporating existing RTL into new SystemC ESL designs.