Tensilica unveils IVP imaging/video DSP IP core - Embedded.com

Tensilica unveils IVP imaging/video DSP IP core


Tensilica, Inc .  has just introduced its IVP imaging and video dataplane processor (DPU) for use in advanced vision based UI applications in mobile handsets, tablets, digital televisiosn (DTV), automotive, video games and computer vision based applications requiring complex image/video signal processing functions.

According to Chris Rowen, Tensilica’s founder and CTO, the IVP DPU is a much needed breakthrough product in terms of energy efficiency and performance in current products and to enable applications never before possible in a programmable device.

He said IVP is supported by a network of third-party application developers who are actively porting leading-edge image applications to the IVP platform including innovative multi-frame image capture and video pre- and post-processing algorithms, as well as established, yet evolving, technologies such as video stabilization, high dynamic range (HDR) image, video HDR, object and face recognition and tracking, low-light image enhancement, digital zoom and gesture recognition.

The IVP’s architecture is tuned imaging and video pixel processing and is capable of a peak performance of 10 to 20x most host CPUs. It is capable of over 130 billion 16-bit RISC-equivalent operations per second, allowing it to tackle the complexity of new image, gesture and video algorithms impossible to run on general-purpose host CPU architectures. It also provides 2 to 4x the performance of any merchant imaging DSP IP core on the market today.

“Consumers want advanced imaging functions like HDR, but the shot-to-shot time with the current technology is several seconds, which is way too long,” said Rowen. “Users want it to work 50x faster.

“The IVP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing, supporting increasing sensor resolutions.”

Tensilica’s IVP is based on a 4-way VLIW (very long instruction word) architecture that delivers high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset.

The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10 GBytes/second of throughput and local memory throughput of 1024 bits per cycle (sixty-four 16-bit pixels/cycle) to keep up with the rapid pace of resolution and frame rate requirements.

The IVP also features many imaging-specific operations to accelerate 8-, 16- and 32-bit pixel data types and video operation patterns. Designed for power efficiency, the IVP is implemented in an automatic synthesis, place-and-route flow in 28nm HPM process, regular VT, a 32-bit integral image computation on 16b pixel data at 1080p30 consumes 10.8 mW. The integral image function is commonly used in applications such as face and object detection and gesture recognition.

The architecture is well matched for high speed processing of complex algorithm kernels such as motion search and normalized cross-correlation, commonly used in high-precision block and feature matching and optical flow.

For a smart motion search on 16-bit data over a 1920×1080 frame with 256×16 pixel search range and 9×3 pixel block size, IVP can achieve a rate of 142 sums of absolute differences per cycle.

In addition, a normalized cross-correlation function on 16-bit pixel data with 32-bit accuracy achieves 1 million 8×8 blocks per second. To ensure that the architecture can be used to run the proprietary imaging and computer vision algorithms many companies have developed, the company makes use of the C programming model common among all Tensilica DPUs.

The company has put together a partner network to enable availability of pre-ported, efficient third-party imaging software including: Almalence, Irida Labs, Dream Chip Technologies and Morpho, Inc.

Tensilica’s IVP DPU can be further customized using Tensilica’s patented processor-generation system. The DPU creation process is totally automated and fully supported by a matching software tool chain. The tool chain includes an optimized compiler, linker, assembler and debugger, plus a matching fast instruction set simulator.

While early-access lead customers have taken delivery of IVP last year, Rowen said the IVP DPU is available for broad licensing now.

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