Tensilica's Atlas reference architecture for dataplane processors ready for evaluation - Embedded.com

Tensilica’s Atlas reference architecture for dataplane processors ready for evaluation

The optimized programmable dataplane processing units of Tensilica's Atlas Reference Architecture are now available for customer evaluation. Atlas supports the 3rd Generation Partnership Project (3GPP) Long-Term Evolution (LTE) standard, as well as other complementary standards such as Evolved High-Speed Packet Access (HSPA+) and WiMAX.

The Atlas Reference Architecture uses the Tensilica ConnX BBE16 baseband DSP core coupled with three function-specific dataplane processor coresĀ  to allow the baseband physical layer (PHY ) system-on-chip developer to create a low power and minimal size PHY system, while enjoying the flexibility of a fully programmable radio, which is needed for competitive multi-standard user equipment devicesĀ  and femtocells.

The ConnX BBE16, introduced February 2010, is the single DSP part of the Atlas reference architecture, as it is built around a core vector pipeline made of sixteen 18bx18b MACs (multiply accumulators). ConnX BBE16 is optimized for performance of DSP kernel operations such as fast Fourier transform and Finite Impulse Response as well as matrix multiplies.

There are several other functions that must be implemented for a fully functional PHY system, and these are better implemented in function-specific DPUs to offer lower power and smaller size and address the control functions required.

The three other Atlas components are:

  • The ConnX Soft Stream Processor (ConnX SSP16), a 16-way SIMD (single instruction, multiple data) baseband core optimized for the processing of soft bits, used for the acceleration of wireless communication PHY routines such as Viterbi, HARQ, and de-rate matching, as well as data manipulation and movement operations.
  • The ConnX Bit Stream Processor (ConnX BSP3), a baseband core optimized for the processing and control of bit streams, used for the acceleration of wireless communication PHY routines such as bit mapping, bit interleaving, and turbo encoding.
  • The multi-standard ConnX Turbo Decoder (ConnX Turbo16), a programmable turbo decoder for LTE and HSPA+ that achieves 150 Mbps decoded bit rate for LTE. The size of this multi-standard turbo decoder is in line with most RTL (register transfer level) hardware implementations in terms of power and area.

The ConnX SSP16 and ConnX BSP3 DPUs are available for evaluation now. The multistandard ConnX Turbo16 DPU will be available for evaluation June 2011.

Tensilica has also launched the ConnX BBE64-128 digital signal processor intellectual property cores for system-on-chip design. It provides over 100 GigaMACs performance in 28nm high-performance process technology.

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