Thanks for the memories, or not?, ESC keynoter explains - Embedded.com

Thanks for the memories, or not?, ESC keynoter explains

Embedded Systems Conference, Boston, Mass. —Today's memory technology gives designers so many choices, and so many tradeoffs. That's the good news and the bad news, and it's only going to get more difficult, as new technologies move to market.

That was the message of a keynote address at the Embedded Systems Conference delivered by Jeff Bader, Director of Marketing for the Embedded Business Group of Numonyx (formed in March 2008 by STMicroelectronics, Intel, and Francisco Partners).

Numonyx Embedded Business Group Director of Marketing
Jeff Bader

Bader said that today's memory situation parallels the history of TV. At first, your choice was simple: to get a TV or not; a few years later, it was just color or black and white; and now, what an array of choices. Similarly, in those old days, the memory-choice options were primarily size, voltage, and boot block configuration; now there's NAND, NOR (in various flavors) and, coming on soon, phase change memory (PCM), ferroelectric RAM (FRAM), and magnetic RAM (MRAM). Add to this serial or parallel interface, package choices, and other options, and it's a designer's wonderland and also headache.

He noted that Moore's law, which has guided memory technology for so many years, may be reaching the end of its roadmap. Why? At 65 nm, a floating gate (incidentally, the size of the Ebola virus or rhinovirs) is storing and managing very small numbers of electrons, approximately 1000 in a NOR cell and 100 in a NAND cell. Multicell designs divide those numbers further, so we're not using many electrons to decide if it's a 1 or 0, he emphasized.

The result, Bader said, is chaos, but he cited author Dr. Tom Barrett: “chaos brings uneasiness, but also opportunity for creativity and growth.” Designers choosing a technology must prioritize parameters relevant to their design, ranking nonvolatility, read and write speed, power, latency, and endurance, among key factors. Vendors, in turn, want scalability for higher density, so there investment has longevity and “long legs.”

Beyond the memory ICs, there are system implications to factor in, such as read performance, endurance (cycles), and retention, as well as requisite system-level support and maintenance for the memory, and architectural continuity. These are obviously quite different for MP3 players compared to embedded devices, and computing functions such as cache and SSD (solid state drive) designs. Time to market and supplier credibility are also non-technical but cortical factors.

There are also key influencers with their own considerations. The software crowd may be concerned with architecture and its impact on reuse; the legal department worries abut risk and intellectual property (IP); purchasing sees cost and supply; marketing thinks about product differentiation and placement; and the QR (quality and reliability) group is concerned about long-term life and standards.

He concluded by asking a rhetorical question: is memory complicated? In a word: yes. There are choices and changes and transitions in all aspects of memory technology. Navigating the memory chaos means that the customer (the designer) must understand usage needs, the true component and system-level costs, and work with a trusted supplier who doesn't fit you into a “one size fits all” solution.

For suppliers, they need to provide technology transparency so customers now what they are getting and where it is going, they need software and systems expertise, and they need a viable roadmap for their immediate supply chain as well as technology longevity.

It's a tall order for all concerned, with conflicting tradeoffs and demands, so it's not a simple decision to make, and it's not going to get easier.

Bill Schweber is the site editor of Planet Analog but is on loan this week to Embedded.com to cover ESC Boston. As a reward, he's collected a lot of pens and gadgets from the show floor. You may contact Bill at .

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