Low-level, sensor signals often generate slow-moving DC signals. For these types of sensors, the delta-sigma, analog-to-digital converter (D–S ADC) eliminates most of the analog input circuitry by providing a high-resolution, low-noise solution. Some systems have multiple sensors, all of which are generating low-frequency signals. In this situation you may need a high-resolution, low-noise ADC that has a multiplexer at its input. An automotive-diagnostic application is an example of a multiplexed sensor system, where numerous small-signal, sensors monitor temperature, tire pressure, airbag readiness, and so forth (see Figure 1 ).
Examples of other sensor-input, multiplexed systems are found in industrial controls, medical, avionics, and process-control applications. Even though the sensors at the input of the multiplexer in these systems present low-frequency (nearly DC) signals, switching from channel-to-channel creates the need for an ADC that is capable of a high-speed response.
In the multiplexed sensor application circuit in Figure 1 , the ADC must be a converter that has multiple channels, zero latency (zero-cycle latency), and low-latency time (settling time). This system requires fully settled output data from each conversion. Before we design such a system we must know something about the signals we wish to digitize. Are they DC signals–perhaps from a number of thermistors or thermocouples? Or are they AC signals, such as two microphones capturing a stereo signal? Or is a combination of both types of signals in the circuit–perhaps the system needs to monitor power supply voltages while it measures power-line frequency as well?
The description of ADC latency implies that a full-scale input signal occurs followed by fully settled output result. This environment is similar to the signal that is presented to the ADC in a multiplexer application. When it comes to A-D converters, there are two types of latency: cycle latency and latency time.
Cycle latency is equal to the number of complete data cycles between the initiation of the input signal conversion and the availability of the corresponding output data. The unit of measure for this type of latency is (n )-cycle latency, where n is a whole number. Cycle latency can be equal to zero if a fully settled conversion is completed before the start of the next cycle. As we will see, the successive approximation register (SAR) ADC is capable of 0-cycle latency as are many D–S ADC.
Latency time is typically viewed as the time required for an ideal step input to converge, within an error margin, to a final digital output value. You would express this error band as a predefined percentage of the total output voltage step. The latency time of an ADC conversion is between the time where the signal acquisition begins to the time that the fully settled data is available to be read from the converter. In contrast to the cycle latency specification, the latency time (or settling time) can never be equal to zero.
Figure 2 shows a frequency versus bits graph of two different converter topologies. In general, delta-sigma converters are used for high-resolution solutions at low data rates. The advantages of the D–S ADCs include low power, high resolution and high stability at a low cost. These advantages are obtained mostly in the digital portion of the circuit. Disadvantages for this type of converter usually include low speed and, in some converters, a non-zero cycle latency.
D–S ADCs are capable of producing from 18 to 31 effective bits. This characteristic reduces the number of analog signal conditioning chips prior to the input of the ADC.
SAR (successive approximation register) converters are used for moderate speeds with medium resolutions (8 to 18 bits). The resolution is generally lower than the D–S ADC, but SAR converters generally operate at higher speeds than D–S ADC. SAR converters are used in many data acquisition applications such as control loops, power monitoring, and low to medium frequency analysis. The advantages of SAR converters include zero-cycle latency and low-latency time. This is achieved with high DC and AC accuracy. The SAR converter fills the gap in resolution and speed above the D–S ADC, but in the middle ground both the D–S and SAR ADC can fill this application space.
Figure 3 shows the basic block diagram for a D–S ADC. The D–S ADC modulator samples the input signal at a very high rate. The digital/decimation filter then takes this sampled data and converts it into a precise digital signal at a much lower rate.
While most converters have only one sample rate, the delta-sigma converter has two: the input sampling rate and the output data rate. For most types of ADCs, such as SAR converters, the data rate and sampling rate are one in the same and one complete code is converted for each input sample. For a delta-sigma converter, many input samples are taken to produce one output code.
In the Figure 3 , we show an analog input signal being converted to a pulse waveform at the output of the modulator. To do this, the delta-sigma modulator uses an input signal quantizer (A/D converter) running at a very high sample rate, producing a steady stream of 1-bit codes that represent the voltage of the input.
Following the modulator is a digital/decimating filter. This module filters and samples the modulator's stream of 1-bit codes. The digital/decimator filter acquires the signals at the output of the modulator. These bits are taken in one at a time and averaged to create a higher bit result. Averaging is really a form of digital filtering, but not the only way to perform digital filtering. Almost all delta-sigma converters incorporate a class of averaging filters called sinc filters, named for their frequency response.
Decimation is the process of reducing a digital signal's output rate to be less than the sampling rate. The way to do this is to discard some of the samples. These samples are discarded in accordance to the Nyquist theorem. Bear in mind, we have not lost any information in this process. It turns out that, instead of calculating numerous samples that we know we will not use, we can simply refrain from calculating them in the first place. The decimator portion of the filter only calculates some of its output samples.
Delta-sigma converter cycle latency
IC designers use multiorder modulators and digital/decimation filters to achieve higher effective resolutions. On a micro level, the multistage digital/decimation filter stages process the modulator bits in a first-in-first-out (FIFO) manner. At the macro level, the cascaded digital/decimation filter stages process the signal in the same manner: FIFO. It's possible to access the output data as each filter stage completes its calculation as a combination of all the filter stages on the output of the converter. If the current and previous modulator conversions are from the same signal, the conversion at the output of the converter will be representative of the input signal. If the current modulator conversions are after a multiplexer change, it is possible that the previous multiplexed input is combined with the current input. This combination produces an output signal that is not fully settled.
Figure 4 shows an example of this type of conversion. In Figure 4 , the digital output performance of a D–S ADC has a 3rd order digital/decimator filter. Although fully settled data from this 24-bit converter is found with the third output data set, the latency is equal to a 2-cycle latency. This important distinction between “2-cycle latency” and three data output results is at the root of the definition of cycle latency. The combination of all three digital stages exists in every output data word. The first data output occurs before the start of the next cycle, hence zero cycles. The second data output occurs before the end of the second full cycle. The fully settled data output is available before the end of the third full cycle, or two cycles of latency.
With a zero-cycle latency ADC, the 1st output data is fully settled. An ADC with zero-cycle latency can also be describe as having single cycle settling or single cycle conversion.
Some delta-sigma converters hide the intermediate or unsettled output results from the user. Figure 5 shows the internal, intermediate conversions of a zerolatency delta-sigma converter. You will notice the hidden conversions , which are an artifact of the order of the digital filter in the delta-sigma converter. The user never sees these hidden conversions. In this example the delta-sigma converter has an internal, 5th order digital filter.
SAR converter cycle latency
Most SAR converters are zero-cycle latency devices. At the input of a SAR converter (Figure 6 ), the input signal first sees a switch at the input of a sample/hold structure. When the switch is closed, the input of the SAR converter has the switch resistance in series with a capacitive array. After an appropriate amount of time for the acquisition of the signal, the sample/hold input switch opens and the converter engages in the conversion process. A few clock cycles later, output data appears on the digital output pin, usually MSB (most significant bit) first. This converter acquires a single sample and outputs the data before starting the next conversion cycles.
Count the sensors
The D–S and SAR analog-to-digital converters both service the application space where there are sensor-output, slow-moving DC signals. If the system has multiple sensors, it's advantageous to use a converter with a multiplexed input. Even though the sensors operate in a low-frequency range, switching from channel-to-channel creates the need for an ADC that is capable of a high-speed response.
Multiplexed sensor application circuits require ADCs that have zero-cycle latency or data available before the initiation of the next conversion cycle. Zero-latency modes exist in many D–S ADCs. This characteristic, along with a high resolution makes this type of device very attractive for this sensor application.
Bonnie Baker is a senior applications engineer at Texas Instruments. She is the author of A Baker's Dozen: Real Analog Solutions for Digital Designers and writes a column for EDN, called “Baker's Best.” You can reach her at email@example.com.
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