The basics of clock jitter in embedded system designs - Embedded.com

The basics of clock jitter in embedded system designs

Clock jitter is deviation of a clock edge from its ideal location. Understanding clock jitter is very important in applications as it plays a key role in the timing budget in a system. It helps the system designers understand the system timing margin.

With the increasing system data rates, timing jitter has become critical in system design, as in some instances the system performance limit is determined by the system timing margin. So a good understanding of the timing jitter becomes very important in system design. Total jitter can be separated into random jitter and deterministic jitter components.

This article does not discuss the composition of jitter. It focuses on the different types of clock jitter (Figure 1 below . Clock timing jitter can be measured in time domain and in frequency domain. Cycle-to-cycle jitter, period jitter and time interval error (TIE) jitter are measured in time domain, where as phase noise and phase jitter are measured in frequency domain.

Figure 1: An example of clock jitter.

Defining the different types of jitter <>Some of the sources of jitter are thermal noise, power supply noise, ground bounce, PLL circuitry, crosstalk and reflections. Defining the different types of jitter There are different types of clock jitter. Here's a discussion of each kind.

Cycle-to-cycle jitter , The cycle-to-cycle jitter measures the change in clock period between any two adjacent clock cycles over 1,000 clock cycles. The cycle-to-cycle jitter RMS measures the standard deviation of the change in clock period measurement between any two adjacent clock cycles over 1,000 clock cycles.

Meanwhile, the cycle-to-cycle jitter peak-to-peak measures the difference between minimum clock period change and maximum clock period change between any two adjacent clock cycles over 1,000 clock cycles.

The cycle-to-cycle jitter measurement is used to determine high frequency jitter in applications as it measures the jitter between two adjacent clock cycles. It is very important to have a small value of cycle to cycle jitter as it impacts the system timing margin.

Period jitter . Shown in Figure 2 below , period jitter measures the maximum deviation of clock period of a clock cycle in the waveform over 10,000 clock cycles.

The period jitter RMS measures the standard deviation of the clock period measurements over 10,000 clock cycles. The period jitter peak-to-peak measures the difference between minimum clock period and maximum clock period measurement over 10,000 clock cycles.

Figure 2: Shown is an example of period jitter measurement of ON Semiconductor's programmable clock NB3N3020.

The period jitter measurement is used to determine low frequency jitter in applications as it measures the jitter by measuring the clock period deviations over 10,000 clock cycles. Period jitter is used to calculate the system timing margin.

Time interval error jitter . The TIE jitter (Figure 3 below ) measures how far each active edge of the clock varies from corresponding edge of an ideal clock. The TIE jitter RMS measures the standard deviation of the timing error. The TIE peak-to-peak measures the difference of the minimum and maximum timing error.

The TIE jitter is important in clock and data recovery (CDR) PLLs to show if the PLL in the CDR is able to track to the incoming data stream. A large TIE jitter shows that the CDR PLL is not able to properly track the variation in the incoming data stream.

Figure 3: An example of the TIE jitter measurement of ON Semiconductor's NB3N3002 clock generator.

Phase noise . Phase noise (Figure 4 below ) is measured in the frequency domain, and is a ratio of signal power to noise power normalized to a 1Hz bandwidth at a given offset from the carrier signal.

Figure 4: A measurement of phase noise and phase jitter

Phase jitter is measured by integrating the phase noise across specified frequency offsets from the carrier signal. Phase jitter measures the amount of energy present in the specified frequency offsets from the carrier signal compared to the energy of the carrier signal by integrating the area under the phase noise plot.

As an example, SONET uses a frequency offset of 12kHz to 20MHz from the carrier signal to integrate the area under the phase noise plot to measure phase jitter. Fiber Channel uses a frequency offset of 637kHz to 10MHz from the carrier signal to integrate the area under the phase noise plot to measure phase jitter.

Baljit Chandhoke is Senior Applications Engineer at ON Semiconductor .

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