The Changing Face of SoC Test - Embedded.com

The Changing Face of SoC Test

As electronic systems become more complex, so do the chips that go into these systems. Higher chip complexity results in more complex and expensive manufacturing testing of these chips. Unfortunately, chip test cost is rising faster than the revenues the chips generate—in other words, test cost is becoming a larger percentage of total chip cost. This article will review the reasons for the rapid rise in chip test cost and what can be done, both from the design and ATE (automatic test equipment) sides, to slow down the runaway cost of testing.

SoC Test is Expensive

System-on-a-chip (SoC) technology has found its way into every facet of our lives, particularly in the consumer and communications arenas. The complexity and speed of SoCs—both of which continue to rise rapidly—has taxed the ability to efficiently and effectively test these chips prior to insertion into their target systems. Among the SoC trends that increase test cost are:

  • An increasing number of logic gates and total transistors, rising faster than the number of device pins, which limits ATE access to silicon cores
  • An increasing number of device pins
  • Higher device speed, both on the chip and through high-speed I/Os
  • More analog content
  • An increase in resistive and speed-related defects, adding test complexity to the traditional 'stuck-at' fault detection
  • Longer test times to account for more complex system conditions.

In his Wescon 2003 keynote speech, Pascal Ronde, VP of Global Sales, Marketing, and Support for Agilent Technologies' Automated Test Group, defines the cost of manufacturing test as:

Cost of Test = (Fixed Costs + Recurring Costs)/(Yield x Utilization x Throughput)

where:

Fixed Costs = Cost of chip tester plus handler depreciated over lifetime plus cost of floor space
Recurring Costs = Utilities, labor, supervision, maintenance, service contracts, engineering support, consumables, and others
Yield = Number of good devices
Utilization = Time the tester is used
Throughput = Number of devices tested per unit time

You can reduce test cost by decreasing the cost of the test system, increasing chip yield (remember that the cost of test is really the cost of testing for good chips only), increasing tester utilization (use it a higher percentage of time), or testing devices faster. ATE manufacturers control test equipment cost, but both they and the vendors of design-for-test (DFT) software tools can affect ATE utilization and throughput. Device yield is a complex parameter, dependent on the silicon process and specific chip-design details.

Cost Reduction via EDA Tools

Built-in Self-Test (BIST)
BIST provides a way of testing multiple cores on a chip. Each core, either a memory block (Figure 1 ) or digital core, can have its own self-test by adding on-chip test circuitry (the BIST controller) to verify the functionality of that core. This also has the advantage of obtaining a third-party core that already has had its BIST designed and verified. BIST may need more test patterns than does ATPG scan, but usually will need less ATE memory than ATPG test. You can also use a BIST controller to test blocks of random logic on the chip. Most chips will combine ATPG and BIST as part of a complete test methodology.

Figure 1:  A BIST controller provides a simple way to test structured blocks such as this SRAM.

Test-Set Compaction
Test throughout is inversely proportional to test time, which scales with the size of the test-vector set you need to test your chip. The higher the test-vector count, the longer the test time and more expensive the test. In extreme cases, very large vector sets may obsolete an existing test system, requiring the purchase or rental of a more expensive tester with expanded capabilities. One way to reduce the number of vectors for given level of fault coverage is through test-set compaction.

Two well-known EDA companies with broad DFT tool suites who offer test-compression tools are Mentor Graphics with TestKompress and SynTest with VirtualScan. Mentor's TestKompress uses the company's Embedded Deterministic Test (EDT) technology by adding on-chip compression logic, located in the test scan path outside of the functional core logic, to a scan-based design, along with a novel deterministic pattern-generation technique. The EDT logic, generated as design-specific RTL code you add to the functional chip's RTL, comprises a decompressor, feeding a large number of internal scan chains from a small number of scan channels, and a selective compactor, which compacts the response to the scan-channel outputs. These blocks allow designers to increase the number of internal scan chains 100X, each 100X shorter than traditional scan chains. The tester sees the 100X reduction in scan-chain length (and accompanying test-time reduction), but still uses the same number of test scan channels and package scan pins that it would for a non-compacted test.

SynTest's VirtualScan uses a similar technique to compact test-vector sets by allowing a tester with a limited number of scan pins to access a large number of short scan chains on the chip. The tool synthesizes a broadcaster, analogous to Mentor's decompressor, and compactor into the chip's scan circuitry along with an enhanced virtual scan ATPG technology to generate the test patterns (Figure 2 ). The original scan chains are split into a number of internal scan chains based on a user-definable “split ratio”. The broadcaster sends data from an external scan-input chain to the internal scan chains and, on the other end, compacts the data into the original number of external scan chains. Through shorter internal scan chains, both VirtualScan and TestKompress significantly reduce the time required to test a chip.

Figure 2:  Test-compaction software such as SynTest's VirtualScan lets you reduce test time by decreasing scan-chain length but keeps the same number of scan channels and pins.

Analog/Mixed Signal Test
By the nature of its design complexity and number of critical operational parameters, on-chip analog circuitry is more difficult to test than is digital circuitry. On the ATE side, what the tester looks for is much different for analog than digital designs. Some EDA vendors have attempted to reduce the problem of analog/mixed-signal (A/MS) test on SoCs by developing digital-test techniques for common analog structures, such as PLLs and ADCs, with mixed results.

One of the Pioneers in this area was Opmaxx, founded in 1996 but since acquired by ATE vendor Credence, who has not chosen to exploit the technology (although structured array vendor Lightspeed Semiconductor does use the Opmaxx technology as part of their test strategy). DFT vendor LogicVision has a software tool, PLL BIST that the company includes in their Embedded Test tool suite. PLL BIST (BIST stands for built-in self-test) is a digital RTL core that goes on-chip for testing PLL parameters including lock range, open loop gain, lock time, and jitter (Figure 3 ), with a connection to the PLL's inputs and outputs through a digital MUX. The tests, being digital, can be part of a chip evaluation or part of a production test with a digital tester using the chip's 1149.1 (boundary scan) port.

Figure 3:  PLL BIST from LogicVision is a digital core you place on your chip to measure PLL parameters using a digital tester.

However, digital testing of analog components on an SoC is limited in scope. At this time, there are no commercialized products for testing other common analog circuits, such as ADCs and DACs. This requires SoC testers to either include analog test capability or to have a separate analog tester available for A/MS chip testing.

Figure 4:  Concurrent test techniques increase the efficiency of expensive ATE by running several tests in parallel on different parts of a chip, each test using different tester resources.

Increasing ATE Efficiency

Concurrent Test
The number of embedded cores in an SoC is rising rapidly—having several dozen on a single chip is not unusual. Different cores require different test strategies and ATE features. For example, the tester may need digital inputs for scan testing, pattern generators for memories, and digitizers and arbitrary waveform generators for analog blocks. Traditional testers test different parts of a chip sequentially, an inefficient way of utilizing ATE resources since it stretches out test time. Figure 4 , taken from Improving Test Efficiency with Concurrent Test, shows how Agilent Technologies uses a 'concurrent test' concept to simultaneously test different chip cores—in this example, two digital tests are conducted along with memory and mixed-signal tests.

The ability to do concurrent testing lies with the ATE vendor's ability to use a multi-port test architecture that uses a per-pin rather than a shared-resource architecture. This allow the tester to supply, on each pin, independent periods, timing, levels, patterns, and sequencing so that that the pin can operate in various modes, including clock, SCAN, BIST-control, functional, APG, digital source, and digital capture. A per-pin capability, found in testers such as Agilent's 93000, allows on-the-fly grouping of pins into virtual ports to test individual silicon cores.

Standards Continue to Help

1149.1 (boundary scan)
JTAG boundary scan (IEEE 1149.1) came about in 1990 as a way of testing individual chips on a PC board. The technology is now used by designers at the chip, board, and system levels for serially feeding test data into an isolated component and then reading the test results. The technology uses four dedicated pins to insert test signals into and out of boundary-scan compatible cores on an SoC. You can also use boundary scan for initiating BIST and accessing BIST results from on-chip silicon cores.

1450 (STIL)
The original STIL (Standard Test Interface Language), IEEE Std 1450-1999, was developed under guidance from the IEEE as a standard way of describing test vectors, providing an interface between ATPG tools and ATE. Besides helping to standardize vector descriptions, STIL files can also compress ATPG generation by up to two orders of magnitude, speeding the flow of design-to-test data. STIL extensions to handle semiconductor design environments, DC-level specification, tester target and flows, test methods, and semiconductor cores are in various stages of development.

P1450.6 (CTL)
Testing embedded cores on an SoC is a difficult problem, due to the complexity of the core's functionality and the task of integrating the core test with the testing of the rest of the chip.

As part of the STIL standard, the IEEE created CTL—the Core Test description Language. CTL is a standard description language containing reusable descriptions, such as a testbench, wrapper and test-environment information, for testing a semiconductor core. As such, CTL provides a standard way to pass core test information from a core provider to a core user, who can then integrate the core into a chip by using the CTL description with various EDA design tools. The language thus gives designers a standard approach for describing DFT structures in core-based SOC designs when generating automatic test programs.

1149.4 (analog boundary scan)
The IEEE 1149.4 mixed-signal test-bus standard defines an analog extension to the 1149.1 boundary scan standard. The mixed-signal standard adds two analog buses to a chip that is 1149.1 compliant (thus increasing the number of test pins from the four needed for the 1149.1 TAP controller to six), and routes the new buses to the chip's analog structures. This lets you insert analog stimuli into and measure analog responses from the chip's analog and mixed-signal blocks. Potential problems with current 1149.4 include concern for the additional area required for analog boundary scan (on the order of 3%, which for most chips is quite small) and high-frequency limitations on the on-chip analog buses.

Complementing Traditional ATE

Several companies, including some of the major ATE vendors, have introduced low-cost alternatives for chip evaluation and low-volume testing. As an example, Teseda has what the company calls a “DFT-focused” tester for doing:

  • DFT-related testing (internal scan, boundary scan, and BIST)
  • Functional testing
  • DC parametric testing.

Designers can use Teseda's lap-top sized machine for low-to-medium pin-count chip and test validation and debug, fault isolation, and engineering sample qualification, at a price an order of magnitude less than what an ATE tester would cost for doing these tasks. This allows you to use the Teseda tester in place of a more expensive ATE tester, freeing the latter for manufacturing test. Competing with Teseda with their own desktop validation tester for chip development, debug, and failure analysis is Inovys.

Finally, the past few years have seen an increase in the number of cooperative ventures between EDA vendors who develop DFT and ATGP tools, and ATE vendors. These cooperative efforts allow both sides to “bridge the DFT/ATE barrier” by imparting tester-specific knowledge with the EDA companies and enhancing ATE-vendor knowledge regarding what to expect from chips designed using specific DFT tools. The end result is a decrease in the time and expense of test-program development, and an increase in the efficiency of running design-specific tests on target ATE machines.

About the Author
Jim Lipman is a consultant providing marketing, writing, and other electronics industry services, specializing in EDA tools and ASIC/SoC design methodologies. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.

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