The Changing Landscape of Design Services -

The Changing Landscape of Design Services


Custom chips are becoming increasingly important in product design. To offer the level of performance and abundance of features the market requires while maintaining product differentiation, the chip design has to be packed with both standard and unique circuitry. Unfortunately, getting such designs done is an increasing challenge.

You have two basic choices for getting a custom chip: design your own or contract for one. Contracting for one typically means going to an ASIC house with a functional spec and letting them do the rest. But that approach is running into trouble on several fronts.

For one thing, going to an ASIC house means that you're limited to whatever technology it has available. In designs where density and performance are not critical, the approach works fine. But if the design needs the best technology available, ASIC houses may not offer access to the technology you need.

Cost is another trouble with the approach, both for you and the ASIC house. Mask sets for 0.13 µm processes are running as high as $750,000. Engineering costs for a multi-million-transistor design can run into tens of millions of dollars because of the multiple teams needed to handle a large design. At these prices, only high-volume products can reasonably recover development costs, reducing the customer base for the ASIC house. Further, the manpower demands limit the number of customers the ASIC house can serve.

Both factors make the traditional ASIC house less of an option now than it was in the past. That leaves the design-it-yourself approach as the more probable choice. Unless you have a large engineering staff, however, you're not likely to be able to tackle the entire job.

Design Services Fill In

This is where design services come into the picture. Figure 1 shows the chip-design process that has remained relatively unchanged for the last 20 years, with the advent of logic synthesis as the major exception. Because of this stability, the industry has been able to foster the evolution of companies that are dedicated to one or more of the design steps.

Some of these companies started as small ASIC houses, designing chips for fabrication in pure-play foundries. In response to competition they capitalized on their strengths, often creating proprietary tools for those aspects of the design at which they were best. As ASIC designs became larger, these companies took the first evolutionary step and sharpened their focus on that one aspect.

Arcadia Design Systems, for example, focuses on optimizing the datapath in high-performance designs such as CPUs. The company can still provide full ASIC development, but it capitalizes on its expertise by offering to handle just the datapath portion of a customer's design.

Other companies chose to focus on an element of the circuit rather than on a step in the design process. These companies offered cores, also called silicon intellectual property (SIP), that customers could use to reduce their overall design effort. Dropping SIP into designs provides entire system functions with minimal customer engineering.

Of course, a blend of these approaches is also possible. Companies such as Silicon Logic Engineering offer both specific design expertise and SIP centered on high-performance computing operations. The company's proprietary tools focus on timing optimization and scan insertion, and its SIP offers floating-point math and DES encryption blocks.

Whatever Happened to SIP?

A few years ago a revolution in chip design was brewing: companies began offering pre-developed pieces of designs as pre-configured cores. These bits of silicon intellectual property (SIP) were supposed to allow chip developers to assemble a large design from existing blocks rather than from scratch. Like Lego brand building tiles, this SIP would let developers easily combine pieces into almost any structure they needed.

Unfortunately, the revolution fizzled. The barrier to entry in the market was too low, allowing dozens of small operations to start offering SIP. The competition caused price erosion. The quality of offerings varied considerably, undermining customer confidence in SIP overall. Further, the SIP was not as easy to drop into a design as expected.

The market quickly segregated into three tiers. The “star” SIP, high-performance elements such as memory and microprocessor cores from companies like Virage Logic and ARM, overcame these early challenges and made for a few successful businesses. Foundation SIP elements, such as UARTs, were absorbed into design libraries. That left the complex SIP, such as USB interfaces, to fulfil the promise of the revolution.

But attrition has taken its toll. Unlike star SIP, the middle tier of SIP is not compelling. It provides valuable functions, to be sure, but it fails to generate brand loyalty because it doesn't control the character of the final chip the way memory and processors do. To make a viable business out of, essentially, commodity products, middle-tier SIP vendors had to offer a broad range of readily applied cores. Companies with only a few cores in hand either folded or merged with others to form a sufficiently diverse product mix.

Even with this aggregation, however, the middle-tier SIP providers are struggling to achieve the critical mass needed to prosper and grow. For instance, InSilicon, a provider of complex SIP for data interfaces, built its product offerings through acquisition, building to more than 50% market share in USB and Ethernet SIP. Even so, its annual revenues of $20M were not enough to sustain growth on its own. The company was recently purchased by Synopsis.

The rest of the SIP revolution seems destined for the same fate. Rather than survive as independent companies, SIP providers are being absorbed into the design services branches of EDA vendors. Like the idealists of many revolutions, they have quietly merged with the establishment.

Next Step in Evolution

The next step in the evolution of design service companies is to drop the full ASIC design service completely and provide only the focus business. This has proven difficult for companies with just an SIP focus (See sidebar, “Whatever Happened to SIP?”) but is working for companies with a design focus. They are making a business out of taking only one step in the design process.

ReShape, for instance, is a design service company that has developed its own tools to automate floorplanning and related activities. ReShape provides its customers with only the physical-design step of the chip-development process, leaving the preceding logic-design and succeeding timing-analysis steps as customer responsibilities.

Few design service companies are as sharply focussed as Reshape, but the trend is clearly toward specialization. With that trend comes an alternative to both the ASIC house model and designing chips entirely in-house: build a chip like you build a house.

In house construction you hire an architect to make a design and a general contractor who assembles a team of specialists (carpenters, plumbers, electricians, and so on) that implement the design. Similarly, in chip design you need both architectural designers and a “general contractor” who can put together the rest of the device by acquiring SIP, as well as specialists for implementation steps such as layout and timing analysis. The general contractor can then take the final design to a foundry for fabrication and contract other specialists for test, packaging, and the like.

In the past, the ASIC house handled everything, serving as logic designer, general contractor, and implementation specialist. With the trends in design services, however, you can now be your own general contractor and have your pick of design specialists, foundries, and packagers. This approach takes only a fraction of the manpower that a full design-it-yourself effort would require. It does, however, require that you know enough about each step to oversee and coordinate the efforts of the specialists.

Yet, even the role of general contractor is being adopted by design service companies. eSilicon, for instance, provides a design service that gives customers choices for the foundry, packager, and the like. The company handles all the coordination of effort and provides the oversight expertise that customers may lack.

Consolidation Pressure Arises

There is a counter-trend, however, that is undermining this design-services model even as it is evolving. The industry's move to 90 nm and smaller technologies is forcing much tighter coordination among the design team participants. As a result, the scattered design elements are being pulled together once again.

The technology trend is forcing tighter coordination in two ways. The first is from the sheer size of designs. Chips are already many tens of millions of gates. At 45-nm geometries (which the SIA expects the industry to reach by 2011) chip density will get to more than 800 million transistors/cm². With that many transistors, the only way chips can be designed is to break the effort into blocks and have teams working in parallel on the design.

The trouble is that those blocks cannot be handled independently if the design is to integrate efficiently. Consider the situation shown in Figure 2 . Each of the blocks is a logical whole that could be designed and laid out independently. If the two registers Reg1 and RegA need to be able to exchange data, however, the independent layouts could end up compromising the design's performance by creating a routing tangle. Restructuring the layouts of the individual blocks to bring the registers into better alignment would facilitate the data exchange in the final arrangement. The only way to find that new structure, however, is if the design teams for the two blocks and for the final layout can all work together.

Figure 2:  These two logic blocks, with inter-block communication requirements between registers (Reg1:RegA and Reg2:RegB), necessitate cooperative efforts between the blocks' design teams and the chip-layout team.

The need for coordination will go deeper, however. The move to 90 nm brings new technical problems to chip design that demand tighter interaction among all the design elements than has been needed in the past. Until now, the move to a new geometry mainly involved a simple geometric scaling. Starting with the 90-nm generation, however, simple scaling won't work. The shift to new materials and the increasing importance of quantum effects means that the design approach must adapt to new requirements. Even the shapes and structures of circuit elements have to change somewhat with each process generation.

Cooperation Fosters Aggregation

These continual changes require close cooperation between tool, library, SIP, and design-service vendors, as well as foundries and process developers. This, in turn, is causing an aggregation of companies. Tool vendors, for instance, are acquiring SIP and design-service vendors in order to tighten relationships as well as to expand their base businesses.

Even the foundries are tightening relationships. TSMC has developed an extensive partnership program that allows it to refer customers to design services with proven expertise on its processes. IBM's foundry operation has gone even further, creating design centers at companies like Cadence. These centers not only have expertise, they have an ongoing relationship with the foundry's engineers and process developers to be able to maintain expertise across process generations.

The conflicting trends of consolidation and specialization are thus altering the landscape of custom-chip design. You need to be prepared to work closely with a group of suppliers rather than a single ASIC vendor, whether you serve as your own general contractor or work through a design service. Suppliers, in turn, will be capable of providing you with multiple variations of the design chain in a matrix of choices. The elements of the matrix may be individual specialist companies such as ReShape or aggregated design services such as Cadence, but flexibility will be the key element. Custom-chip developers need the ability to choose the right combination of SIP, design assistance, and manufacturing process, without compromise.

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