The definitive guide to ARM Cortex-M0/M0+: Low-power benchmark setup -

The definitive guide to ARM Cortex-M0/M0+: Low-power benchmark setup


Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Jack Gannsle wrote, these books will “…give you the insight you need to be productive on real projects.”

CHAPTER 19. Ultralow-Power Designs (Cont.)  

19.7.5 The Test Setup

The overview of the setup can be summarized as:

  • MCG running in BLPE (Bypassed Low-Power External) state. External crystal oscil- lator running at 8 MHz is used with PLL and FLL disabled and bypassed.

  • For first step of our experiment, the microcontroller uses Normal Run and Normal Stop. The system runs on 8-MHz clock frequency.

  • Then we enhance the design to use Very Low-Power Run (VLPR) and Very Low-Power Stop (VLPS) modes to further reduce the power.

  • The wake-up source selected is the Low-Power Timer (LPTMR) module.

  • UART0 is used and is configured to run at 38,400 bps.

The setup of the MCG is easy. The control code is already included in the default. “system_MKL25Z4.c “. We only need to select the define option in this file: 

The code to get the system running is as follows. Please note that at the start of the test program, a UART input function is called so that the test does not start until it has received a character from the UART interface. This prevents the board from being locked out completely by the low-power mode and allow the program flash to be reprogrammed (see safe mode operation in 19.5.2).

Once this is working, the “void Low_Power_Config(void) ” function is updated to include the additional enhancement:

  • To enable the use of VLPR and VLPS modes, we need to reduce the clock frequency of the system from 8 MHz to a lower frequency at 4 MHz or lower. A frequency value of 1 MHz is selected.

  • To save more power, the flash memory is turned off during sleep (this is referred as Flash Doze feature in Freescale document).

  • Turn off internal oscillator.

  • Enable the very-low power modes by programming to the System Mode Controller (SMC) module.

The modified “void Low_Power_Config(void) ” function is as follows.


19.7.6 Measurement Results

After the test is created, several measurements were made (Table 19.4). Please note that the measurements should be made without debugger connected. Note: Due to the limitation of the multimeter used and other potential factors in the setup (e.g., potentially activities of the onboard SDA debugger chip might have affected the debug operation state), the results shown here might not be accurate.

The sleep current of 1.27 mA seems a bit high. With a CR2032 coin cell of 225 mAh, this gives only 177 h of operations (just over 1 week). However, the KL25Z data sheet quotes the power of using an external 4 MHz crystal adds around 228 µA electric current. Since we are using an 8-MHz crystal, the actual power used by the external crystal oscillator can be quite significant. In addition, the 8-MHz clock routing paths to peripherals (e.g., clock buffers and capacitance of clock lines) can also contribute to the higher power.

In order to double check how the system power can be further reduced, the test setup is modified to use the internal 4-MHz RC oscillator. The “SystemInit() ” function is edited to add a new clock setup so that the system is Started with MCG unit in BLPI (Bypassed Low Power Internal) mode. The processor and bus clocks are reduced to 1 MHz by the clock dividers (Table 19.5).

To help investigate the power activities, a 10-Ω resistor can be used to connect along the voltage supply connection and the voltage across the resistor can be measured with an oscilloscope (Figure 19.13). However, due to the small electrical current in this test, the result cannot be read from the graph accurately.

Figure 19.13. Measurement of power pattern.

Assume that most of the time the microcontroller is sleeping (using 0.04 mA), this now gives us 5500 h, or over 200 days of battery life from a single CR2032 battery.

Additional power saving could be possible by reducing the active cycles. For example, by using interrupt-driven mechanism to output the text string into the UART, instead of polling-based UART function, could help. However, an experimental trial of changing the printf message to just output one character do not seems to be able to reduce the power consumption. This potentially highlight that the majority of the power is not consumed by the processor or the UART, but could be by other components inside the chip.

The active cycles can also be reduced by compiler optimizations and software optimizations. Also, potential delay could also be resulted if some of the bus clock frequency and memory clock speed are set too low. It is important to carefully investigate the clock frequency requirements for each part of the design.

If the application is not using the UART interface, potentially we can run the system at a much lower clock frequency. According to the datasheet, the electric current of the oscillator can be reduced to ~ 0.5 µA if using a 32 KHz. Also, with such arrangement, the RTC can be used for the periodic 1-Hz interrupt generation instead of the Low-Power Timer module.

Do not forget that we have not utilized all the low-power modes in the KL25Z design yet. There are a number of other low-leakage power modes available and can further reduce the idle/sleep current.

Stay tuned for the next installment: An Example of Using the Low-Power Features

About the author
Joseph Yiu is a Senior Embedded Technology Specialist at ARM Ltd. in Cambridge, UK. He joined ARM in 2001 and has been involved in a wide range of projects including development of ARM Cortex-M processors and various on-chip system level and debug components. In addition to in-depth knowledge of the processors and microcontroller system design, Yiu also has extensive knowledge in related areas including software development for the ARM Cortex-M microcontrollers, FPGA development and System-on-Chip design technologies. He received his BEng. in Electronics Engineering from City University of Hong Kong and an MSc. In Microelectronics Systems Design from University of Southampton.

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