Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Embedded.com blogger Jack Gannsle wrote, these books will “…give you the insight you need to be productive on real projects.”
In a series of installments, we offer an excerpt of Yiu's book focusing on the low-power features of these processors and use of those features in building ultralow-power designs:
Elsevier is offering this and other engineering books at a 30% discount. To use this discount, click here and use code ENGIN317 during checkout.
Adapted from The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, by Joseph Yiu (Newnes).
CHAPTER 9. System Control and Low-Power Features
9.5 Low-Power Features
A number of low-power features are available in the Cortex-M0 and Cortex-M0+ processors. In addition, microcontroller vendors usually also implement a number of low- power modes in their Cortex-M0/M0+-based microcontroller products. This section focuses mostly on the low-power features provided by the Cortex-M0 and Cortex-M0+ processors. Details for microcontroller-specific low-power features are usually available in user manuals or application notes available from the microcontroller vendor Web sites, or in example software packages. Some examples of using device-specific low-power features are covered in Chapter 19.
In general, the Cortex-M processors include the following low-power features:
Two architectural sleep modes: normal sleep and deep sleep. The sleep modes can be further extended with vendor-specific speed control features. Within the processor, both sleep modes behave similarly. However, the rest of the microcontroller can typically reduce power by applying different level of device-specific power reduction methods based on these two modes.
Two instructions for entering sleep modes: WFE and WFI. Both can be used with normal sleep and deep sleep modes.
Sleep-On-Exit (from exception) feature: allowing interrupt driven applications to stay in sleep mode as often as possible.
Optional Wake-up Interrupt Controller (WIC): this optional feature allows the clocks of the processor to be completely turned off during sleeps. When this feature is used with state retention technology, found in certain modern silicon implementation processes, the processor can enter a power-down state with extremely low-leakage power, and it is still able to wake up and resume operations almost immediately.
Low-power design implementation: various design techniques were used to reduce the power consumption as much as possible. Since the gate count is also very low, the static leakage power of the processor is tiny compared to most other 32-bit microcontrollers.
In addition, various characteristics of the Cortex-M processors also help to reduce power consumption:
High performance: the Cortex-M0 and Cortex-M0+ processors performance is often several times higher than many popular 8-bit/16-bit microcontrollers. This allows the same computational tasks to be carried out in shorter time and the microcontroller can stay in sleep modes for longer period of time. Alternately, the microcontroller can run at a slower clock frequency to perform the same required processing task to reduce power.
High-code density: By having a very efficient instruction set, the required program size can be reduced and as a result you can use a Cortex-M0 or Cortex-M0+-based micro- controller with smaller flash memory to reduce power consumption and cost.
Because the processor is only a small part of a microcontroller, to get the best energy efficiency and maximum battery life out of a microcontroller product, it is necessary to understand not only the processor but also the rest of the microcontroller. Most microcontroller vendors provide application notes and software libraries to make this easier for software developers.
9.5.2 Sleep Modes
Most microcontrollers support at least one type of sleep mode to allow the power consumption to be reduced when no processing is required. In the Cortex-M processors, sleep mode support is included as part of the processor architecture.
The Cortex-M Processors have two sleep modes defined in the architecture:
Chip designers can add additional control registers and additional power control capability to further extend the number of sleep modes. The exact meaning and behaviors of these sleep modes depend on the implementation of the microcontrollers. Microcontroller vendors can use various power saving measures to reduce the power of the microcontroller during active states as well as sleep. Typically, the method for reducing power during sleep includes the following:
stopping some or all of the clock signals
reducing the clock frequency to some of the logic
reducing voltage to various parts of the microcontroller
- turning off the power supply to some parts of the microcontroller
The sleep modes can be entered by three different methods:
execution of a WFE instruction
execution of a WFI instruction
using the Sleep-On-Exit feature (this is covered in detail in Section 9.5.5)
When entering sleep, whether the normal sleep mode or the deep sleep mode will be used is determined by a control bit called SLEEPDEEP. This bit is located in the System Control Register (SCR), see Section 9.2.6 of the SCB region, which contains the control bits for the low-power features of the Cortex-M Processors (see Table 9.9). Users of CMSIS compliant device drivers can access to the SCR using the register name “SCB->SCR”.
Different sleep modes and different sleep operation types can result in various combinations as shown in Figure 9.4.
Figure 9.4. Combination of sleep modes and sleep entering methods.
9.5.3 Wait-for-Event and Wait-for-Interrupt
There are two instructions that can cause a Cortex-M processor to enter sleep: WFE and WFI.
Enter sleep conditionally
Suitable for idle loops or idle threads in real-time operating system
Enter sleep unconditionally
Suitable for interrupt driven applications
Both instructions can be used to enter either normal sleep or deep sleep modes depending on the value of the SLEEPDEEP bit in the SCR. The WFE can be woken up by interrupt requests as well as events and debug requests, while WFI can be woken up by interrupt requests or debug requests only (see Table 9.12).
Architecturally, a DSB instruction should be used before executing WFE/WFI. However, with the simplistic nature of the pipeline in the Cortex-M0 and Cortex-M0þ processors, omitting the memory barrier would not cause any issue. But if the software needs to be reusable on other ARM! processors, the DSB instruction should be used.
Table 9.12: WFE and WFI wake-up characteristics
When the WFE instruction is used to enter sleep, it can be woken up by interrupts as well as a number of different events including:
New pending interrupts (only when SEVONPEND bit in SCR is set)
External event requests
Inside a Cortex-M processor, there is a single-bit event register. When the processor is running, this register can be set to one when an event occurs and this information is stored until the processor executes a WFE instruction. The event register can be set by any of the following events:
An interrupt request arrives and need servicing
Exception entrance and exception exit
New pending interrupts (only when SEVONPEND bit in SCR is set), even if the interrupts are disabled
An external event signal from on-chip hardware (device specific)
Execution of an SEV (Send Event) instruction
When multiple events occur while the processor is awake, they will be treated as just one event because the event register is only one bit.
This event register is cleared when the stored event is used to wake up the processor from a WFE instruction. If the event register was set when the WFE instruction is executed, the event register will be cleared and the WFE will be completed immediately without entering sleep. If the event register was cleared when executing WFE, the processor will enter sleep, and the next event will wake up the processor, with the event register remaining cleared. The operation is summarized in Figure 9.5.
Figure 9.5. WFE operation.
The WFE is useful for reducing power in polling loops. For example, a peripheral with event generation function can work with WFE so that the processor wakes up upon completion of peripheral’s task, as shown in Figure 9.6.
Figure 9.6. WFE usage.
Since the processor can be woken up by different events, the processor must still check the peripheral status after being woken up to see if the task has completed.
If the SEVONPEND bit in the SCR is set, any new pending interrupts, generate an event and wake up the processor. If an interrupt is already in pending state when WFE is entered, a new interrupt request for the same interrupt does not cause the event to be generated and the processor will not be woken.
The WFI instruction can be woken up by interrupt requests that are a higher priority than the current priority level, or by debug requests (see Figure 9.7).
Figure 9.7. WFI operation.
There is one special case of WFI operation: During WFI sleep, if an interrupt is blocked by PRIMASK, but otherwise has a higher priority than the current exception priority level, it can still wake up the processor, but the interrupt handler will not be executed until the PRIMASK is cleared.
This characteristic allows some parts of the microcontroller to be turned off by software (e.g., peripheral bus clock), and the software can turn it back on after waking up before executing the interrupt service routine. This is covered in the next section (Section 9.5.4).
Copyright © 2016 Elsevier, Inc. All rights reserved.
Printed with permission from Newnes, a division of Elsevier. Copyright 2016. For more information on this title and other similar books, please visit www.newnespress.com.