The definitive guide to ARM Cortex-M0/M0+: Using low-power features -

The definitive guide to ARM Cortex-M0/M0+: Using low-power features


Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Jack Gannsle wrote, these books will “…give you the insight you need to be productive on real projects.”

CHAPTER 19. Ultralow-Power Designs (Cont.)  

19.8 Example of Using Low-Power Feature on LPC1114

19.8.1 Overview of LPC1114FN28

While the LPC1114 product series is not the lowest power Cortex!-M0/Cortex-M0þ microcontroller from NXP, it is an interesting product as it is available in DIP package. It means even hobbyists can construct low-power circuit boards at home (e.g., on breadboard). While there are plenty of other microcontroller development boards that can plug onto breadboard, often those boards do not allow users to isolate the power of the microcontroller from the power supply of the other components. So that adds to complexity when creating simple low-power systems.

The LPC111x supports four power modes (Table 19.6).

The LPC1114FN28 device has an internal 12-MHz RC oscillator (trimmed), and a programmable low-power watchdog oscillator. In addition, there is an external crystal oscillator. The clock generation unit of the LPC111x is shown in Figure 19.14.

Figure 19.14. LPC111x clock generation unit. Image from LPC111x User Manual.

The power management of the LPC111x is controlled by a number of registers (Table 19.7).

The details of these registers can be found in NXP LPC111x User Manual.

19.8.2 First Experiment — Running at 12 MHz with Internal and External Crystal

In the first test, a small experiment is carried out to compare the power consumption when running the system at 12 MHz, with internal and external crystals.

In the project, we set the CLOCK_SETUP macro in system_LPC11xx.c to 0. And handle all the clock initialization in the main program code if needed. We added a C macro USE_EXT_CRYSTAL to select between internal crystal and external crystal.

After compiling and executing the program, some measurements are carried out (Table 19.8).

From here, we can see that you can have lower power with an external crystal oscillator. Of course, this result is device-specific and in general the result can be affected by many factors like the crystal component being used and if there is any special low-power feature for either oscillators.

19.8.3 Second Experiment — Running at Reduced Frequencies of 1 MHz and 100 KHz

We can save a large portion of power by reducing the operation frequency. In the LPC1114, we can do this by programming the System AHB clock divider (LPC_SYSCON->SYSAHBCLKDIV). Please note this can have an impact to the timer’s programming if we need to wake up the system at the same 1-Hz rate.

Most of the codes are similar from the previous example, with the addition of:

And the timer configuration code needs to deal with the new preprocessing macros. 

After doing the changes, we can measure the result and compare to the previous 12-MHz setup (Table 19.9). All results here are based on using of external 12-MHz crystal as source.

Here, we can see that at low-clock frequencies (using clock divider or prescalar), the reduction of power is not linear. So even the operating frequency is reduced by 10 from 1 MHz to 100 KHz, the active current reduction is only around 11%.

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19.8.4 Additional Improvements

Some simple additional improvements can help. In the project you might have noticed that we have an empty function call “void Low_Power_Config(void).” Here we add the addition code to reduce the power further.

After doing the changes, we can measure the result and compare to the previous 100 KHz setup (Table 19.10). Again, all results here are based on using of external 12-MHz crystal as source.

So these minor changes give approximately 10% reduction in power.

19.8.5 Using Deep Sleep on LPC1114

While we can get to just w1 mA operation, this is not good enough for some of the ULP applications. You might notice that so far the deep sleep mode feature has not been enabled in the previous examples. To use deep sleep mode, the program code quite a few changes because of several restrictions on the LPC1114 deep sleep mode support:

  • In deep sleep mode, the only available clock source is the watchdog oscillator. It is very low power, but can have up to `40% tolerance of the clock frequency value.

  • In deep sleep mode, the timer interrupt will not operate and it can only be wake up by one of the Wake-Up interrupts.

There are a couple of other areas we need to take care of:

  • Due to the inaccuracy of the clock source, it is not ideal for UART communication. As an experiment, it is still usable by tuning the UART baud rate setting based on the actual frequency, but this is not suitable for product production.

  • When the LPC1114 microcontroller is in deep sleep mode, it will not be able to be wake up by a debugger and therefore could lock out the device from flash program updates.

Depending on the microcontroller product, there can be special boot mode(s) to disable execution of application programmed in the flash memory. In the NXP LPC111x, port 0 bit 1 can be used in such situation. The NXP111x has an In-System Programming (ISP) feature to allow the flash to be programmed using the boot loader and the serial port. By pulling bit 1 of port 0 to low at power up reset, the ISP program in the boot loader will be executed. You can use the ISP feature to update flash, or connect the in-circuit debugger to the microcontroller and update the flash.

Before using the deep sleep mode, we need to configure a number of registers as shown in Table 19.7, and then program the System Control Register (SCB->SCR) to enable the deep sleep mode. We also need to program the NVIC, timer, watchdog clock, and start logic.

Start logic on the NXP LPC111x is triggered by I/O port activities. So we use the timer match event output to drive an I/O port output, and then use this signal level to trigger the wake up as shown in Figure 19.15.

Figure 19.15. Deep sleep wake up mechanism used for LPC1114 example.  

In this example, we are going to toggle pin 9 of port 0. The processor is put into sleep mode most of the time, and woken up only when the 16-bit timer 0 reaches the required value.

The result is very encouraging (Table 19.11 and Figure 19.16).

To get a better view of the result, we connect a 10-U resistor in series with the voltage supply of the microcontroller and measure the voltage across. The waveform obtained is shown in Figure 19.16.

Figure 19.16. Test result using deep sleep mode.  

Although there are some limitations for the deep sleep mode in LCP1114, if the system design does not have to wake up at a precise time interval, you can still utilize the deep sleep mode to get very low idle current. After the system woke up, you can optionally turn on and switch to an alternate clock source (e.g., external crystal for higher frequency accuracy) for the data processing, and switch that back off before returning to sleep.

About the author
Joseph Yiu is a Senior Embedded Technology Specialist at ARM Ltd. in Cambridge, UK. He joined ARM in 2001 and has been involved in a wide range of projects including development of ARM Cortex-M processors and various on-chip system level and debug components. In addition to in-depth knowledge of the processors and microcontroller system design, Yiu also has extensive knowledge in related areas including software development for the ARM Cortex-M microcontrollers, FPGA development and System-on-Chip design technologies. He received his BEng. in Electronics Engineering from City University of Hong Kong and an MSc. In Microelectronics Systems Design from University of Southampton.

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