The definitive guide to ARM Cortex-M0/M0+: Wake-up operation - Embedded.com

The definitive guide to ARM Cortex-M0/M0+: Wake-up operation

Editor's Note: In designing deeply embedded systems, engineers face ongoing tradeoffs between power and performance. The rapid emergence of opportunities for personal electronics, wearables and Internet of Things (IoT) applications only exacerbates challenges in reducing power while enhancing performance. The ARM Cortex-M0 and Cortex-M0+ processors have emerged as a leading solution, providing the core for a broad range of microcontrollers designed to meet tough requirements for low-power, high-performance operation. In The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition, Joseph Yiu offers a comprehensive view of these processors. As Embedded.com blogger Jack Gannsle wrote, these books will “…give you the insight you need to be productive on real projects.”

CHAPTER 9. System Control and Low-Power Features (Cont.)

9.5.4 Wake-up Conditions
When a WFI instruction is executed or when the processor enters sleep mode using the Sleep-On-Exit feature, the processor stops instruction execution and wakes up when an (higher priority) interrupt request arrives and needs to be serviced. If the processor enters sleep in an exception handler, and if the newly arrived interrupt request has the same or lower priority as the current exception, the processor will not wake up and will remain in pending state. The processor can also be woken up by a halt request from debugger, or by a reset.

When the WFE instruction is executed, the action of the processor depends on the current state of an event latch inside the processor:

  • If the event latch was set, the event latch will be cleared and the WFE completes without entering sleep.

  • If the event latch was cleared, the processor will enter sleep mode until an event takes place.

An event could be any of the following:

  • an interrupt request arriving which needs servicing

  • entering or leaving an exception handler

  • a halt debug request

  • an external event signal from on-chip hardware (device specific)

  • if the SEVONPEND (Send-Event-On-Pend) feature is enabled and a new pending interrupt occurs

  • execution of the SEV (Send Event) instruction

The event latch inside the processor can hold an event which happened in the past, so an old event can cause the processor to wake up from a WFE instruction. Therefore usually the WFE is used in an idle loop or polling loop as it might or might not cause entering of sleep mode.

WFE can also be woken up by interrupt requests if they have a higher priority than the current interrupt’s priority level, or when there is a new pending interrupt request and the SEVONPEND bit (Send event on pending) is set. The SEVONPEND feature can wake up the processor from WFE sleep even if the priority level of the newly pended interrupt is at the same or lower level than the current interrupt. However, in this case, the processor will not execute the interrupt handler and will resume program execution from the instruction following the WFE.

The wake-up conditions of the WFE and WFI instructions are illustrated in Table 9.13.

Table 9.13: WFI and WFE sleep wake-up behavior  

The wake-up behavior of Sleep-On-Exit is same as WFI sleep.

Some of you might wonder why when PRIMASK is set, it allows the processor to wake up but without executing the interrupt service routine. This arrangement allows the processor to execute system management tasks (for example, restore clock to peripherals) before execute the interrupt service routine, as shown in Figure 9.8.


Figure 9.8. Use of PRIMASK with sleep.  

In summary, the similarities and differences between WFI and WFE are shown in Table 9.14.

Table 9.14: WFI and WFE comparisons  

Next Page >>

9.5.5 Sleep-On-Exit Feature
One of the low-power features of the Cortex-M processors is called Sleep-On-Exit. When this feature is enabled, the processor automatically enters a WFI sleep mode when exiting an exception handler and if no other exception is waiting to be processed.

This feature is useful for applications where the processor activities are interrupt-driven. For example, the software flow could be like the flow chart in Figure 9.9.


Figure 9.9. Sleep-On-Exit program flow.

The resulting activities of the processor are illustrated in Figure 9.10.


Figure 9.10. Sleep-On-Exit operation.

The Sleep-On-Exit feature reduces the active cycles of the processor and also the energy consumed by the stacking and unstacking of processes between the interrupts. Each time the processor finishes an interrupt service routine and enters sleep, it does not have to carry out the unstacking process because it knows that these registers will have to be stacked again when another interrupt request arrives next time.

The Sleep-On-Exit feature is controlled by the SLEEPONEXIT bit in the SCR. Setting this bit in an interrupt driven application is usually carried out as the last step of the initialization process. Otherwise the processor might enter sleep during the initialization of the processor, if an interrupt occurs during this stage.

9.5.6 Wake-up Interrupt Controller
Designers of microcontrollers using Cortex-M processors can optionally include a WIC
in their design. The WIC is a small interrupt detection logic that mirrors the interrupt masking function in the NVIC. The WIC allows the power consumption of the processor to be further reduced by stopping all the clock signals to the processor or even putting the processor into a state retention state. When an interrupt is detected, the WIC sends a request to a power management unit (PMU) inside the microcontroller to restore power and clock signals to the processor, and then the processor can wake up, resume operation and process the interrupt request.

An important advantage of the WIC feature is that it is transparent to the software. The WIC itself does not contain any programmable registers, it has an interface that couples to the NVIC of the Cortex-M0/M0þ processor and the interrupt mask information is transferred from the processor to the WIC automatically during sleep. In some cases (depending on the design of the microcontroller device) the WIC is activated only in deep sleep mode (SLEEPDEEP bit is set), and you might also need to program additional control registers in a device-specific PMU in the microcontroller to enable the WIC mode deep sleep.

The WIC enables the Cortex-M processors to reduce standby power consumption using a technology called State Retention Power Gating (SRPG). With SRPG, the leakage power of a sequential digital system during sleep can be minimized by powering off most parts of the logic, leaving a small memory element in each flip-flop to retain the current state. This is shown in Figure 9.11.

When working with the WIC, a Cortex-M processor implemented with SRPG technology can be powered down during deep sleep to minimize the leakage current of the microcontroller. During WIC mode deep sleep, the interrupt detection operation is handed over to the WIC. Since the state of the processor is retained in the flip-flops, the processor can wake up and resume operations almost immediately. The operation is illustrated in Figure 9.12. In practice, the use of SRPG power down can increase the interrupt latency slightly, depending on how long it takes for the voltage on the processor to be stabilized after the power-up sequence.


Figure 9.11. SRPG technology allows most parts of a digital system to be powered down.


Figure 9.12. Illustration of WIC mode deep sleep operations.

Not all Cortex-M processor based microcontrollers support the WIC feature. The reduction of power using the WIC depends on the application and the semiconductor process being used.

When the WIC mode deep sleep is used, the SysTick timer is stopped and it would be necessary to set up a separate peripheral timer to wake up the processor periodically if your application requires an embedded OS and need the OS to operate continuously. Also, when developing simple applications without any embedded OS and if WIC mode deep sleep is required, and if a periodic interrupt is needed, then it would be necessary to use a peripheral timer for periodic interrupt generation instead of the SysTick timer.

Please note that in the Cortex-M0 and Cortex-M0þ processors, the WIC can be used in both sleep and deep sleep modes. In the Cortex-M3 and Cortex-M4 processors, the WIC feature is only available in deep sleep.

About the author
Joseph Yiu is a Senior Embedded Technology Specialist at ARM Ltd. in Cambridge, UK. He joined ARM in 2001 and has been involved in a wide range of projects including development of ARM Cortex-M processors and various on-chip system level and debug components. In addition to in-depth knowledge of the processors and microcontroller system design, Yiu also has extensive knowledge in related areas including software development for the ARM Cortex-M microcontrollers, FPGA development and System-on-Chip design technologies. He received his BEng. in Electronics Engineering from City University of Hong Kong and an MSc. In Microelectronics Systems Design from University of Southampton.
Copyright © 2016 Elsevier, Inc. All rights reserved.
Printed with permission from Newnes, a division of Elsevier. Copyright 2016. For more information on this title and other similar books, please visit www.newnespress.com.

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