The derring-do of hardware design and debug -

The derring-do of hardware design and debug

In many ways, the work of the hardware developer faced with designing a printed circuit board and then debugging it reminds me of the derring-do swordplay in those classic swashbuckling movies of the last century (see Video) . In these movies, the hero is usually contenting with not just one opponent, but many, as he duels up and down staircases and across roofs, and in the process using elaborate, daring tricks to defeat them.

Likewise, in printed circuit boards, the hardware engineer is faced with a variety of challenges: from the customer who wants a smaller but more densely populated board, but with the highest possible performance, and from package and chip designers pushing the limits of the signal integrity the design needs.

At the debug stage the engineer is faced with multiple hard-to-diagnose glitches that may be due to a board signal trace problem, an IC, or the chip package interface. And like the movie swashbuckler busy with multiple opponents, the hardware engineer more often than not finds new ones have jumped out of the bushes in the form of software bugs disguised as hardware problems.

In this week’s Tech Focus Newsletter are a number of design articles and blogs on such challenges, how developers solved them, and some of the tools and techniques used to defeat the barriers to a working design. Among the board level design articles dealing with such issues as debugging system crashes, reducing noise corruption, and PCB reliability assurance, my Editor’s Top Picks are:

Tips about printed circuit board design. In this three part series, Walt Kester provides a compendium of tips and hints that will help embedded systems developers speed the design of the printed circuit boards upon which their designs are based.

Tips on building & debugging embedded designs. I n this two part series, Jack Ganssle, passes on some tips about embedded systems design from his experiences as both a designer and a manager of hardware and software projects.

Saving your embedded PCB design with forensic technology, which deals explains how to deal with miniscule defects on a printed circuit board that cause sub-system failures and the techniques for closer inspection that can often reveal the culprit after conventional techniques fail. .

Ultra-fine pitch devices pose new PCB design issues. As the industry marches on towards more miniaturization, the trend is more toward system-on-chip than it is toward more shrinking. The result is more IC packages with pitches of 0.3mm and less, presenting significant challenges to printed circuit board designers.

For more adventures about hardware board design and debug, be sure to register to attend the 2014 DesignCon, Jan. 29-31, 2014, in Santa Clara, Ca. There you will be able to choose from among 140 papers and classes , where most of those on board design and debug issues are sorted into four tracks: Optimize Chip/Package/Board Co-design , PCB materials and processing characterization , Apply PCB design tools and methodologies , and Power integrity in power distribution networks. Of these my Must Attend class and session recommendations are:

Differential signal routing for PCB designers. Mehlmauer of Broadcom and Charles Pfeil of Mentor Graphics deal with routing PCB differential signals, how to manage signal integrity effects, and understanding at which data rates they are important to manage. Typical concerns include total length matching, via effects, impedance discontinuities, breakout length, phase matching, via stubs, and fiberweave.

Practical Design Considerations for Dense, High-Speed, Differential Stripline PCB Routing. Erik Daniel, Michael Degerstrom, Barry Gilbert and Chad Smutzer of the Mayo Clinic describe a method by which to de-skew within board pin-fields to minimize or eliminate the jog-outs due to length mismatch caused by pin-pair offset and stripline direction, thus simplifying PCB signal routing.

Make Predictable PCB Interconnects for Data Rates of 50 Gbps and Beyond. In this session participants from Rambus, Inc., Altera Corporation and Simberian, Inc. will contribute their thoughts about what it takes for successful design with 50 Gbps interconnect design by making use of practical dielectric and conductor roughness models and understanding the importance of loss separation in conductor roughness and dielectric models.

In addition there will be a panel session on How PCB Design is Changing: Simulation and Design Techniques, that will include the following speakers: Eric Bogatin, Bogatin Enterprises; Filip Demuynck, Agilent Technologies, Inc.;Scott McMorrow,Teraspeed Consulting Group; Chudy Nwachukwu,, Isola Group; Lee Ritchey, Speeding Edge; and David Wiens, Mentor Graphics, Inc.

Do you have some interesting stories about PCB and other hardware design and debug challenges you would like to share? If so, contact me and we can work together to create a brief blog or a design article for Or simply write a brief summary of your experiences in the comment section below. Site Editor Bernard Cole is also editor of the twice-a-week newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to, or call 928-525-9087.

See more articles and columns like this one on up for the newsletters. Copyright © 2013 UBM–All rights reserved.

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