Large arrays of clearance holes in powerplanes can have a dramatic effect on the behavior of high-speedsignals. Signal integrity is a growing problem for designersbecause new designs are calling for components with higher andhigher pin counts that must be connected using vias to access theinternal layers of printed-circuit boards (PCB). The proper designof the hole and pad stack results in high-yield power planes whilepreserving the quality of very fast signals routed through theseareas. Failure to account for the proper clearances results in lowPCB yields due to short circuits, unsatisfactory impedancevariations in transmission lines, or both. A typical power-planestructure results when a high-pin-count ball-grid array (BGA)package is mounted on a multilayer PCB.
Figure 1: Illustration of a trace routed over the typicalhole pattern created in a power plane by a BGA
Clearance holes in the power planes allow room for the holesdrilled through the PCB when creating vias to connect to the BGApins. The PCB fabrication process used to build the PCB determinesthe size of the clearance holes. The parameters of a multilayer PCB(A-F in Figure 2) determine its clearance hole.
Figure 2: Anatomy of a drilled, plated hole in amultilayer PCB
The maximum wander of the drilled hole (C in Figure 2) is thesum of the accuracy of the following factors:
- Drill in finding the true hole location
- Ability of the fabrication process to register the inner-layerimages
- Registration accuracy of pairs of inner layers
- Amount that inner-layer patterns shift with respect to eachother during lamination
- Dimensional stability of the raw materials used to build thePCB
- Amount that the drill may be deflected from the vertical as itpasses through the laminate
- Accuracy with which outer-layer images can be registered toinner-layer patterns.
These factors become more important as the PCB size increases.When creating the tolerance budget for a particular PCB design, itis recommended that the panel size to be used in manufacturing beadjusted according to the fabrication specifications.
The dimensions of the plated-through hole in Figure 2 are asfollows:
- A = B + two times the plating thickness (normally 1-milminimum)
- C = A + two times the drill and registration tolerances(usually 6-mils for 18×24″ panels)
- D = C + two times the minimum annular ring (usually2-mils)
- F = D + two times the clearance to nearest copper in plane orsignal layers (usually 5-mils)
- For a 12-mil-drilled hole, the clearance hole (F) is 38-milsand the capture pad (D) is 28-mils
- For a 24-mil-drilled hole, the clearance hole (F) is 50-milsand the capture pad (D) is 40-mils.
From this dimensional analysis, we see that the 50-mil-pitchBGAs routed using 12-mil vias resulted in a web of 12-mils, morethan enough to preserve the impedance of a 5-mil trace passing overit. This combination of trace width, via size, and clearance padsize results in a buildable PCB that is both electrically sound andeasy to fabricate. The clearance pad dimension (F) describes acylinder that passes through every layer of the PCB. To preserveproper clearances, all copper in every layer must remain outside ofthis area. Therefore, traces cannot be wider than the web width. Ifmore than one trace is routed between two pins, the combined widthand separating space cannot exceed the web width.
In a 1mm or 40-mil-pitch BGA package, the clearance hole for a12-mil drill still needs to be 38-mils. The remaining web is only2-mils. Clearly, the impedance of traces passing through an arraywith these dimensions experiences a significant increase inimpedance. More importantly, traces cannot be wider than this 2-milweb to satisfy clearance rules in signal layers.
The current generation of computers and networking equipmentfrequently uses 1mm BGA packages. To achieve reasonable yields atPCB fabrication, one or more of the dimensions shown in Figure 2must be decreased. This is often achieved by building PCBs onpanels smaller than 18×24″. When the PCB size requires the use of18x24″ or larger process panels, 1mm packages cause decreasedyields, compromised signal integrity, or both.
Figure 3: Edge Rate Erosion Due to Signal Reflection fromImpedance Change in a Typical 1mm BGA Array
Edge erosion on the switching edge is caused by the increase intrace impedance as the signal travels through the BGA array andproduces a positive reflection of part of the incident signal. Theenergy reflected from the impedance change slows down the switchingedge. While in most systems this effect can be ignored, the 50psecor higher time delay may be unacceptable for gigabit and abovesignals.
Remedies for Fine-Pitch BGA Clearance Problems
When 50-mil-pitch BGAs are used, it is possible to choosedimensions that result in uniform trace impedances under the BGAand create a manufacturable PCB. As the pitch of a BGA decreases,the amount of space available to create satisfactory webs anduniform impedance traces diminishes. At 1mm (40-mils), it ispossible to achieve the desired result by reducing the size of thePCB panel. In this case, the additional space for a web is gainedby reducing the other allowances. As the pitch of a BGA is reducedto below 1mm, such as with uBGAs and chipscale packages, there isnot enough copper to preserve the web or provide a good partner fortraces routed through the array.
The solution for ball pitches below 1mm is to use a combinationof through-hole vias and blind vias. Since the device's power pinsneed to be connected using through-hole vias, the power-pinassignments on the package are spread out enough to allow adequatewebs in the power planes. The signal pins are then routed on signalplanes accessed using only blind vias.
Blind vias can be laser drilled to almost any depth, so onemight expect to be able to use them to route signals to any buriedsignal layer. Unfortunately, plating copper into blind vias placesa limitation on how deep it can be drilled. Successful platinglimits a blind via to a depth no greater than its diameter.Therefore, a 5-mil blind via can only route signals 5-mils deep.This restriction places a practical limitation on routing withblind vias. In most cases, laser-drilled blind via technologylimits this routing method to the outer layers and the first buriedlayer.
Devices with pin pitches of less than 1mm that can be routedusing layers one and two (or n and n-1, for the general case) mayuse a combination of through-hole drilled vias for the power pinsand blind vias for signal routing. As a practical matter, thislimits the total pin count to less than 100. Memory IC areas arethe primary locations where this form of routing works well.
Calculating the effects of clearance hole arrays in power planeshelp ensure proper design of hole and pad stacks, resulting inhigher-yield power planes and greater signal-qualitypreservation.
About the Author
Lee W. Ritchey, B.S.E.E., owns Speeding Edge, a consulting firm specializing in high-speed design consulting and training. He has served on Printed Circuit Design's editorial review board and regularly contributes to a variety of publications. Ritchey has taught his High-Speed Design course to more than 3000 engineers and designers in several countries and is a regular lecturer at the PCB Design Conferences, the IPC conferences, and the UC Berkeley Engineering Extension.