The Evolution of On-Chip Test IP - Embedded.com

The Evolution of On-Chip Test IP

While new and ever-faster microprocessor architectures helped fuel digital system design during the 1990s, the rate of new processor architectures has slowed dramatically. FPGAs have become the primary hardware contribution in the majority of today's system designs. The programmable nature of FPGA allows for inclusion of a wide variety of IP (intellectual property). Test IP has quietly become a popular form of FPGA IP. Understanding what test cores exists, tradeoffs, and how test IP can be used in conjunction with test equipment helps teams meet their development schedules.

Many types of traditional test equipment now have equivalent IP blocks that can be inserted into FPGA designs. The appropriate use of these test IP cores can accelerate development schedules in two ways. First, the test IP allows some lengthy simulation test bench tasks to be done much more quickly in-circuit at real-world speeds. Second, test IP enables teams to find in-circuit design defects more quickly minimizing validation time.

Logic analysis cores are the most prevalent IP cores in the FPGA industry. Both Xilinx and Altera offer logic analysis cores. Altera's ELA, Embedded Logic Analyzer, and Xilinx's ILA, Integrated Logic Analyzer, offer many traditional logic analysis features for in-circuit debug. The structure of the analyzer core is similar to a simple external logic analyzer. The core contains two main blocks, a comparator for triggering and a storage buffer for capturing the trace. Additionally, each vendor provides a viewer to analyze the captured data. The cores can be inserted into the FPGA design pre-synthesis or post-synthesis. Users specify probe points and the tools route a connection between these nodes and the inputs of the core. Once the core is in the design and the design running in-circuit, a trigger specification is downloaded via JTAG.

When the core triggers, a real-time trace measurement is made and the captured information is stored using blocks of internal FPGA memory. A JTAG cable is used to pass information from the logic analysis core to a viewer hosted on a PC. Logic analysis cores, the viewer, and the associated tools to insert the cores are bundled together as a toolset. The toolset is licensed on a subscription basis and there are no royalty fees for the cores. The entire solution costs well below $1000 and can be used on as many projects as desired.

Because FPGAs are reprogrammable and other system hardware components are not, FPGAs tend to get their final definition after all of the other component definitions are finalized. This tends to constrain how many FPGA pins can be dedicated for debug visibility. Incremental functionality after the initial product release is often delivered by enhancements to the FPGA and usually consumes more pins. This further constrains the availability of debug pins for observability of internal events using external test equipment. When are internal logic analysis cores effective? Internal logic analysis cores are particularly useful for pin limited designs, as the cores do not require any additional pins for real time trace. The cores provide real-time measurements by keeping track of measured nodes at each clock cycle and storing this value to memory. The cores provide effective information to determine the behavior of internal circuits without using any external pins.

What are the tradeoffs in using internal analysis cores? There are several. The first is that inclusion of the core will change the timing of the FPGA design. The design now includes a new block that must be placed and routed. Design teams often mitigate this issue by picking a part and core combination where the core consumes roughly 5% or less of the resources on the FPGA. Once the design is debugged, ripping out the test IP will change the timing of the FPGA design. Not wanting to change the timing of the design once it works properly, design teams tend to leave the core in the final shipping design so that timing remains constant.

The second tradeoff comes from the mode used to collect trace data. While traditional logic analyzers offer state and timing modes, internal logic analysis cores sample exclusively in state mode, synchronous with a clock provided by the FPGA circuit being measured. Internal logic analysis cores provide a correct view of the design at each clock cycle. But, they can miss subtle events that occur between clock cycles. Third, internal logic analysis cores store the trace using internal FPGA memory¬ómemory that the design team may want to use for the design. Because of the limited amount of internal FPGA memory available for design and debug, design teams are typically limited to shallow internal logic analysis trace depths.

The second type of test IP provides the ability to easily manipulate the stimulus to the design. A good example of this is the Xilinx VIO (Virtual Input Output). The VIO core provides capabilities previously delivered by external pattern generators with sequential parallel vectors to stimulate the design. With a VIO core, design teams can drive internal FPGA nodes deep in the design. With the combination of ILA and VIO, users of Xilinx FPGAs can create in-circuit test benches that have little or no external pin requirements. Creating a test bench includes connecting a VIO output core to the inputs of the design and an ILA to the outputs of your design. This debug methodology offers a speedy alternative to exhaustive simulation. Additionally the VIO core allows the team to change node values to stress a design to determine its ability to recover.

The most advanced FPGAs include dedicated silicon for high-performance processor cores. PowerPC PPC 403 cores come standard in Xilinx Virtex 2 Pro parts and ARM7 cores come standard in Altera Excalibur parts. These cores contain on-chip test circuitry that provides processor control, debugger support, and real-time processor trace measurements accessible over the same JTAG connection that controls other test IP.

Will on-chip test IP replace traditional external test equipment? Not in the near future. There are certain classes of debug issues that can be solved effectively using test IP. Other classes of debug issues, especially those that require an asynchronous view of FPGA and surrounding system behavior, will continue to be best solved using external test equipment. Perhaps the most compelling debug capabilities come from mixing the two technologies. Internal test IP typically includes a port to send a trigger signal to external test equipment as well as another port that accepts a trigger sent from external test equipment. This can be very powerful for solving complex debug problems.

Figure 1:  On-chip test IP can work together with external test equipment. In this case, an Agilent logic analyzer can monitor signals on a memory bus and tell an internal logic analysis core when to take a trace measurement.

A design team within Agilent Technologies recently encountered a problem in their FPGA-based memory controller that occurred very infrequently. They hooked up an logic analyzer to the memory bus and found they could trigger on the problem, but because the FPGA had no spare pins, the team could not use the logic analyzer to look internally to the FPGA to determine the cause of the problem. The team then inserted an ILA core into the design. While they now had internal visibility to track the root cause of the problem, they no longer could trigger on the memory bus condition that indicated there was a problem. The team was able to quickly resolve the issue when they combined the two approaches. They used a logic analyzer to trigger on the memory bus glitch and then had it send a signal to the ILA core to take a trace. Using this method, they were able to quickly isolate the design defect.

Test IP cores and methodologies will continue to become more capable over time. Increasingly large and more complex system FPGAs with limited external visibility and control will be the driving force behind this transformation. This evolution will continue to work synergistically with external test equipment as vendors driving these technologies partner to develop better-integrated solutions.

About the Author
Joel Woodward received his BSEE from Brigham Young University and a Masters in Business Administration (MBA) from Regis University. For the past 14 years Joel has worked at Agilent Technologies (Hewlett-Packard) as both an engineer and manager on development tools within the EDA and test and measurement industries and is currently a logic analysis product manager. His outside interests include photography and hiking.

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