The future of the PCIe interconnect bus - Embedded.com

The future of the PCIe interconnect bus

Looking at the range of recent news, product introductions, design and technicalarticles included in this week’s Embedded.com Tech Focus newsletter ,i t is hard to believe there was once a time when there was no PCI Expressnor any of its Peripheral Component Interconnect progenitors.

Shortly after the Intel x86 architecture exploded into the market placein the mid-1970s, all there was in the many homebrew personal computers andsingle board computers developed for industry was the S-100 bus, originally nothing more than the pins of the Intel 8080 run out onto the backplaneto form the single system bus.

But after about five years its dominance evaporated. In 1981 IBM bulldozedits way into the one computing market segment it did not dominate – personalcomputing – with the IBM PC AT and its Industry Standard Architecture(ISA), which also quickly became widely used in embedded single boardcomputing. 

ISA’s dominance as well was short lived. By 1987, Intel engineers developedthe PCI bus to replace it. And now, remarkably, 25 years later, PCIe dominatesvirtually every segment of computing where a high performance interconnectbus is necessary.

Part of its longevity is the flexibility of the original PCIe specificationand the foresight of the engineers who developed it. But much is also owedto the companies that make up the PCI SIG, who haveadapted and extended the standard into a wide range of applications. In additionto the recent design articles included in this week’s Tech Focus newsletter ,other articles that reflect its flexibility and usefulness to developersinclude:

Making the shift to optical interconnect with PCIe Gen3
WhyPCIe-Based Systems Need Multicast
Using multi-root (MR) PCIe to extend nextgen multi-host switch fabrics
Using an interface wrappers to simplify implementing PCIe on FPGAs 

Indicative of the ubiquity and vitality of the PCIe bus across the embeddedsystem infrastructure are some recent conference and technical journal papersI have come across, including:

Speedy bus mastering with PCI Express
A PCIe Hot-Plug mechanism for a Linux ATCA control system
Bus mastering PCI Express in an FPGA
DirectGPU/FPGA communication via PCI Express 

This is not to say that PCIe does not have its limitations and is notwithout serious competitors in many important segments of the market. In“Sub-microsecondinterconnects: PCIe, RapidIO and other alternatives,” Sam Fullermakes the important observation that much as there are different forms ofprocessors that are optimized for differing applications, interconnects arealso designed and optimized to solve different connectivity problems.

Typically an interconnect will solve the problems it was designedfor very well and can be pressed into service to solve other problems, butit will be less efficient in these applications ,” he writes. Technologiessuch as PCI Express and 10G Ethernet are certainly not going away any timesoon, according to Fuller, but they also will not be the foundation for futuretightly coupled computing systems.

As the systems you are designing move to applications requiring fasterand more reliable high speed interconnects, you will no doubt be consideringa variety of high speed, low latency alternatives. I would like to hear fromyou in the form of comments on the site, emails , contributed articlesor blogs about how you are addressing these issues.

Embedded.com Site Editor Bernard Cole is also editor of thetwice-a-week Embedded.comnewsletters as well as a partner in the TechRite Associates editorialservices consultancy. He welcomes your feedback. Send an email to , or call928-525-9087.

See more articles and column like this one on Embedded.com. Signup for the Embedded.com newsletters .Copyright © 2013 UBM–All rights reserved.

1 thought on “The future of the PCIe interconnect bus

  1. Great article, but I think we should that “PCIe bus” is misnomer. PCIe is more of a point-to-point link, it is not a bus. Great data bandwidth but high latency.

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