The need for wafer level chip scale packaging in SRAMs

While talking about the future of wearable technology, Ralph Osterhout (CEO, The Osterhout Design group) made a crisp and relevant observation: “What won’t work is a bulky device that distances people from their environment. If you’re talking about something that makes you look like a hammer-head shark with wires? Then, no. It’s not going to work.” ( source) This clearly indicates the future course of innovation in wearable technology. It’s loud and clear that to be successful, a wearable electronic item has to be small while maintaining performance.

To reduce footprint and, consequently, overall board-space, microcontrollers are migrating to smaller process nodes every successive generation. At the same time they are evolving to perform more complex and powerful operations. The need for increasing cache memory becomes imminent as operations become more complex. Unfortunately, with every new process node, increasing the embedded cache (embedded SRAM) becomes challenging for multiple reasons including higher SER, lower yield, and increased power consumption. In addition, customers also have customized SRAM requirements. For an MCU maker to provide all the possible cache sizes would require them to have a portfolio that is too big to be manageable. This drives the need for limiting the embedded SRAM on the controller die and instead caching through an external SRAM.

However, using an external SRAM challenges the very process of miniaturization as external SRAMs occupy significant board space. Because of its six-transistor structure, reducing an external SRAM size by migrating it to smaller process nodes will invite the same problems that plague miniaturizing embedded SRAMs.

This brings us to the next alternative to this age-old problem: reduce the chip package to die size ratio in the external SRAM. Typically the size of a packaged SRAM chip is many times (up to 10x) the size of the die. One prevalent way of addressing the problem is to not use a packaged SRAM chip at all. Instead, it makes sense to take the SRAM die (1/10th the size of an SRAM chip) and package it together with the MCU die using sophisticated multi-chip packaging (MCP) or 3D packaging techniques (also known as SiP or System-in-Package). However, this method requires significant investment and is viable only for the largest of manufacturers. From a design stand-point, it also reduces flexibility since the components in a SiP aren’t easily replaceable. For example, if there is a new technology SRAM available, we cannot easily replace the SRAM die in the SiP easily. To replace any die within the package, the entire SiP would have to be re-qualified. Re-qualification requires reinvestment and additional time.

So is there a way to save on board-space, while keeping the SRAM out of the MCU and not getting into the hassles of MCP? Going back to the die to chip size ratio, we do see a scope for significant improvement. Why not check whether there can be a package that can stick closer to the die? In other words, if you can’t eliminate the package, reduce the size ratio instead.

The most advanced approach currently is to reduce the packaged die size by using WLCSP (wafer level chip scale packaging). WLCSP refers to the technology of assembling individual units in packages after dicing them from a wafer. The device is essentially a die with an array pattern of bumps or balls without using any bond wires or interposer connections. By specification, a chip scale package part has an area that is at the most 20% larger than the die. Today the process has reached a level of innovation whereby fabrication plants produce CSP devices without increasing the area of the die (only increasing the thickness slightly to fit the bumps/balls).


Figure. Wafer level chip scale packaging (WLCSP) offers the most advanced approach to reducing packaged die size. The WLCSP shown here was developed at Deca Technologies and does not increase the area of the die comprising it. (Source: Deca Technologies/Cypress Semiconductor)

CSP has certain advantages over the bare die. CSP devices are easier to test, handle, assemble and reword. They also have enhanced thermal conduction characteristics. And when dies shift to newer process nodes, the size of the CSP can be standardized while dies shrink. This ensures that a CSP part can be replaced by a newer generation CSP part without the any of complications associated with replacing a die.

It is quite clear that these space savings are significant when it comes to the requirements of wearables and portable electronics. For example, a 48-ball BGA used by memories in many wearable devices today has the dimensions 8mm x 6mm x 1mm (48mm3 ). By comparison, the same part in a CSP type package has the dimensions 3.7mm x 3.8mm x 0.5mm (7mm3 ). In other words, it is possible to reduce the volume by 85%. This savings can be used to reduce the portable device’s PCB area and thickness. For this reason, there is renewed demand for WLCSP-based devices beyond just SRAM from wearable and IoT (Internet of Things) manufacturers. For more information on designing with WLCSP, designers can refer to Getting Started with Chip Scale Packages.

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