The Risk/Reward Realities of Chip Development - Embedded.com

The Risk/Reward Realities of Chip Development

Semiconductor companies face a growing gap between design complexity and conventional signoff methodologies. However, the semiconductor industry too often focuses on minimizing time-to-tapeout, despite a growing awareness that traditional verification methods are proving inadequate to uncover design faults prior to silicon manufacturing. In contrast, the incremental time spent on enhanced design verification and analysis offers dramatic downstream benefits—not only in reducing the risk of high re-spin costs but also in allowing designers to optimize designs for greater yield, higher performance and a consequent shorter overall time-to-profit.

With the increased cost of failure in today's business climate, semiconductor companies face a growing need for new development models that reduce the risk of failure and ensure a greater overall profit potential. By re-examining the critical cost components of development, manufacturers can make more effective decisions in moving to these new models.

Evolving Development Model

Today's market realities have dramatically reshaped basic assumptions for product development and profitability. At the macro level, changing demand and increased competition for more sophisticated electronic products continue to compress traditional product lifecycle curves (Figure 1 ) with implications that touch all facets of development. Because product end-of-life can occur much more quickly than in the past, IC manufacturers accustomed to years of high-margin return during a product's mature phase find much more limited revenue opportunities. In this context, delayed delivery of new ICs not only is certain to shorten revenue, but also can cause the manufacturer to miss a product window entirely. For the manufacturer, however, the relative impact of changing lifecycles depends on cost management and development decisions made early in development.


Figure 1:  Changing demand and market competition have compressed product lifecycles, resulting in shorter duration revenue opportunities

As with any manufacturing model, IC product development is reflected in steadily accumulating expenses, sharply punctuated by major cost events associated with prototype manufacturing and volume production. At launch, a major IC design effort incurs costs that today can easily exceed $1M for computer systems and software including EDA tools. For a modest 10-person project staff, ongoing expenses can exceed $200K/month, assuming a fully loaded cost of $250K/year per staff member. As development continues, the associated cost curve continues to move steadily downward toward tapeout for prototype manufacturing (Figure 2 ).


Figure 2:  Idealized cost curve for design phase

With the migration to advanced nanometer-technology nodes, manufacturing brings costs that continue to rise substantially with each new technology generation. Mask sets alone cost $500 to $800K for 130 nm technologies, and twice that for emerging 90 nm technologies. In addition, wafer costs typically run at least $50K per lot. Manufacturers also face non-recurring expenses for test setup, including test fixtures, load boards, and test development and characterization, along with direct unit costs associated with packaging and handling.


Figure 3:  Idealized cost curve for project achieving fully functioning silicon at first-pass prototype manufacturing, permitting immediate entry to volume production

In the best case, where prototype manufacturing returns fully functioning silicon on the first pass, the combined cost of these various charges can still exceed $1M. In a highly idealized flow (Figure 3 ), a design would move immediately from prototype manufacturing into volume production, where costs for a relatively modest 100K production run, for example, could exceed $2M from die, package, and test costs as follows:

  • Die costs , which can range from about $5 to $20/die, depend on the size of the die and the wafer, wafer cost, and yield. A die size of 1cm² is considered the largest cost-effective size for 8-inch wafers. For a typical 25-layer CMOS process, wafer costs can run about $2750. Die yield is a complex function of manufacturing parameters but ranges from 40% to over 90% for mature technologies. These costs combine in the following equation:

  • Package costs , which vary 0.5/pin to 5.0/pin, reach nearly $8 per unit for a relatively simple wire-bonded 512-pin package, even assuming a conservative per-pin cost. Advanced technologies such as flip-chip can bring costs ranging from $20 to well over $100 per unit. Furthermore, these advanced packaging technologies can also introduce additional upstream design requirements that can increase the total chip-design effort by as much as 50%.
  • Test costs depend on test time at rates ranging from $50/hr to $500/hr, typically translating into a unit cost about $4 for a nominal test time at mid-range rates. Highly integrated parts, such as memory-intensive system-on-a-chip (SoC) devices, for example, can require multiple insertions in different types of specialized test equipment, often creating a throughput bottleneck and significantly boosting test cost.
Impact of Nanometer Technology

In this highly idealized flow, a design moves with no delays at each major transition—from design to prototype manufacturing; from prototype manufacturing to volume production; and from volume production to revenue-producing delivery. In this best-case scenario, profits begin accumulating within a relatively short time after volume production begins (Figure 4 ). In reality, of course, IC companies face continuing challenges in reducing breakeven time—a problem exacerbated by the complexity of advanced nanometer-process technologies.


Figure 4:  Idealized revenue growth and profit for an IC achieving first-silicon success and immediate volume sales

At increasingly dense nanometer-process technologies, electrical and physical phenomena exhibit significantly greater effect on circuit performance. In fact, interconnect delay, coupling capacitance and power-network IR voltage drop already dominate gate delay at the 130 nm process node and threaten to overwhelm gate delay in emerging 90 nm technologies (Figure 5 ). Nevertheless, conventional signoff methodologies rely on traditional gate-level verification tools that are unable to accurately detect these nanometer effects. Traditional signoff methods ignore the very effects that cause nanometer designs to fail. Because of this gap between analysis requirements and traditional verification capabilities, the semiconductor industry, on the average, needs two or more silicon re-spins for over 50% of advanced designs, according to research firm Collett International.


Figure 5:  Increasing impact of nanometer effects on circuit performance with more advanced nanometer technologies

The increased delays and costs associated with silicon re-spins dramatically impact time-to-market and time-to-profit. Along with the more obvious cause-and-effect nature of these delays illustrated in Figure 6 , each silicon re-spin sets the IC manufacturer further back in their ability to deliver the working samples needed to lock in crucial design wins. In the worst case, the manufacturer may miss the window of opportunity, but even in the best case, the manufacturer faces correspondingly longer delays to reach a break-even point until volume sales eventually begin.


Figure 6:  Impact of silicon respins on time-to-market and time-to-profit
Corrective Strategies

In the absence of detailed analysis capabilities, IC designers are forced to rely on a combination of diagnostic and preventative measures. Engineers can explore failed silicon using diagnostic equipment such as focused-ion beam (FIB) devices that adds several hundred dollars an hour in direct equipment costs as well as lost productivity while engineers spend valuable time working at offsite FIB services. Increased use of flip-chip technologies requires even more expensive approaches such as laser voltage probe (LVP) or picosecond image circuit analysis (PICA) systems able to handle backside probing of nanometer-geometry devices with multiple metal layers.

In an attempt to avoid nanometer-induced failures entirely, engineers typically take a preventative approach, building in increased guard banding of the timing design, physical design, or both. By broadening timing or physical margins, however, guard-banding methods limit performance and silicon efficiency. Instead of achieving faster, smaller, and lower-cost ICs, designers end up with slower chips whose larger die area translates into lower per-wafer yield—resulting in a smaller number of less competitive devices.

In the end, neither preventative nor diagnostic methods are able to directly address design problems caused by nanometer effects. A direct solution requires the ability to analyze designs at the transistor level, where nanometer effects occur, using detailed post-layout parasitics, which model these effects. Traditional Spice or even fast-Spice tools lack the speed or capacity to effectively handle post-layout, transistor-level analysis of complex designs except through limited critical-path analysis. Because circuits can be affected by interactions from elements outside the path itself, this kind of limited analysis can easily miss significant nanometer effects.

Predictive Approach

Reliable prediction requires detailed analysis of large blocks and even on the complete design—a problem well beyond the ability of conventional verification tools. Based on hierarchical analysis engines and advanced parasitic-reduction techniques, the newest generation of tools, such as Nassda's HSIM and LEXSIM, are able to achieve the kind of full-chip, transistor-level, post-layout analysis required to accurately predict nanometer effects. Although this additional analysis will slightly extend time to tapeout, the ability to reduce or eliminate the risk of silicon re-spins more than compensates for slightly longer design time, offering cost savings that heavily outweigh those incremental engineering costs.

Besides eliminating potentially damaging costs, detailed predictive analysis provides substantial direct benefits to the overall profit equation. As noted earlier, the global application of guard-banding methods inevitably lowers profit by degrading performance and yield. With the availability of more sophisticated nanometer-analysis capabilities, however, engineers can optimize IC designs, applying guard-bands only in specific circuits that truly require additional margin. Design optimization improves yield, lowering per-unit costs, while increased performance enables premium pricing, boosting per-unit revenue. In the microprocessor market, for example, when clock rates doubled from 500 MHz to 1 GHz, the price of the faster chips shot up ten-fold. This combination of faster revenue growth and shallower cost curves can dramatically shorten the time to a break-even point (Figure 7 )—softening the blow of shrinking product lifecycles.


Figure 7:  Impact of design optimization on time-to-profit

As IC manufacturers face increased design complexity and more advanced nanometer technologies, the impact of silicon failure threatens to become more devastating. Besides introducing significant direct and indirect costs, the effects of non-functioning silicon can ripple through partner supply chains, affecting relationships and future opportunities. By taking the time to reduce the risk of silicon failure through more sophisticated nanometer-analysis methods, IC designers can meet tight delivery schedules with optimized silicon, dramatically improving the overall profit potential for more highly differentiated ICs.

About the Author

Simon Young is product line director at Nassda Corporation and has over 20 years of experience in design and design automation. He was director of product line management at Silicon Metrics from 2000 to 2001. Prior to that he spent five years as product line manager for reliability assurance at Synopsys. He also held positions at Mentor Graphics, GenRad, Texas Instruments, and Intel. Young received his PhD from Imperial College in the U.K.

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