The role of phase-change memory in automotive OTA firmware upgrades - Embedded.com

The role of phase-change memory in automotive OTA firmware upgrades

Here is how phase change memory (PCM) benefits the MCUs in performing OTA firmware upgrades in zone- and domain-based ECU architectures.

The part 1 of this article series explained how memory impacts compute performance, power consumption, reliability and cost of zone and domain systems in automobiles. Now, let’s talk about the role and impact of one particular kind of nonvolatile memory (NVM)—phase change memory (PCM)—in a key feature and benefit to MCUs: over-the-air (OTA) firmware upgrades, also known as firmware over-the-air (FOTA) upgrades.

The OTA firmware upgrades are an important capability for zone- and domain-based applications at a time when the automotive market is evolving faster than ever. New features and upgrades need to be rolled out quickly for vehicles in the field, and here, the OTA firmware upgrades assure a low-cost upgrade mechanism.

The zone and domain ECU architectures require an OTA firmware upgrade capability that is fast and works without application downtime.

The OTA firmware upgrade architectures

Two types of OTA firmware upgrade approaches are common, and they differ in whether they optimize cost or performance, reliability and efficiency. A single application-image-based implementation (Figure 1-a) is the more economical approach as it uses roughly half the nonvolatile memory required to implement the dual application-image-based or A/B swap-based system (Figure 1-b).

Figure 1-a: A single image-based implementation is more economical. Source: STMicroelectronics

Figure 1-b: A dual image-based implementation requires roughly 2x nonvolatile memory. Source: STMicroelectronics

With roughly 2x the necessary nonvolatile memory, the dual application-image approach “protects” the original firmware so that the vehicle/ECU can continuously migrate to the new firmware and operate between versions without any downtime. Moreover, in case of problems, the earlier version is still available in NVM and offers a roll-back option. It’s a more commonly used architecture in automotive applications—at the cost of doubling the size of flash compared to the application size.

Beyond memory cost, another important aspect of OTA upgrade implementation is the time to update the application. Time directly impacts the user and how long dealers spend downloading the updates into vehicles. Updating the flash with the new image is a two-step process: erase and write. Furthermore, erase time can be four to five times longer than the write operation. So, fast upgrades require optimizing both write and erase times.

The OTA firmware upgrades with PCM

PCM memory, like that in Stellar SR6 MCUs, changes the way OTA firmware upgrades are implemented by addressing the above-mentioned challenges. PCM has two physical cells per logical bit that work together to provide high reliability and long retention time at high temperature, as mandated in automotive applications. During normal program execution, the second physical bit is the inverse of the first bit, also known as the differential mode. Figure 2 illustrates how PCM works in normal operation.

Figure 2: This is how phase change memory (PCM) works during the normal operation. Source: STMicroelectronics

When implementing an OTA firmware upgrade, the second physical cell does not need to store the inverse data and can store the new data, as Figure 3 suggests. This configuration is also known as the single-ended mode.

Figure 3: This is how PCM works during the OTA firmware upgrades. Source: STMicroelectronics

The PCM cell size is much smaller compared to other embedded nonvolatile memory technologies. So, two physical cells don’t require to double the physical space compared to other architectures.

Therefore, the availability of the second physical cell essentially doubles the available memory size during an OTA firmware upgrade. For instance, if an MCU has 20 MB of total PCM memory, it can support 20 MB application size. Then, during an OTA upgrade, the MCU’s available memory doubles to 40 MB. So, the MCU can store two images of 20 MB each. This feature addresses the need to double the size of memory to support OTA upgrades.

In addition, the existing firmware can continue to execute during the OTA upgrade, eliminating downtime. Equally valuable, as the existing firmware is kept during the upgrade, the system can roll back the firmware in case of any error. Once the OTA firmware upgrade process is complete, the PCM goes back to the differential mode. Combined, these capabilities give PCM the cost benefits of a single-image OTA firmware upgrade architecture with all the feature advantages of the dual-image, A/B swap architecture.

PCM has other advantages, too. Without the need for an erase operation before writing, PCM provides faster write operations than NOR flash. Hence, PCM shrinks OTA firmware upgrade time, improving user experience and reducing service cost. These capabilities also lower the power consumption for the firmware upgrade. As a result, if the updates are downloading while the vehicle is operating, the firmware upgrade draws less power from the vehicle’s battery.

Here, it’s worth mentioning that traditional A/B swap or dual-image-based implementations store both old and new images even after the OTA upgrade process is complete. Ideally, both images are only needed to ensure no-downtime during the OTA upgrade and to offer the potential to roll back the upgrade to the previous version in case of errors. As mentioned earlier, PCM is unique in its support for this flexibility without wasting memory capacity unlike other memory types.

PCM can also support traditional A/B swap/dual-image implementation if both images need to be maintained even after the OTA upgrade process. In this case, though the application size will be half of total PCM like an implementation with embedded flash; PCM still provides the advantage of faster writes, as it doesn’t require a pre-write erase.

Why PCM matters in zone and domain MCUs

Zone and domain architectures offer big advantages by improving system performance and reducing system complexity and vehicle weight. They impact weight mostly by reducing the number of wiring harnesses. On the other hand, the integration of functions and capabilities in these architectures require higher compute capability compared to traditional ECUs.

To get the best out of these architectures, code in NVM must be fast enough to minimize wait states. Data in NVM should also be fast to improve system performance. To avoid needing an external EEPROM, the data in NVM should emulate a fast EEPROM without degrading endurance and neighboring memory cells. Low-power operation is also of primary importance as it directly impacts an electric vehicle’s single-charge range. In addition, fast programming, both at the factory as well as over-the-air for upgrades is vital to manage costs.

Unfortunately, the existing NOR flash architectures are less than ideal in most of these aspects. Manufacturers have been able to improve the speed of some NOR flash types, but those improvements are petering out at technology nodes below 40 nm.

Now, as zone and domain MCUs based on 28-nm technology are coming to market, providing a small footprint and cost-effective silicon demands new NVM technology that is scalable. Phase-change memory addresses these challenges by offering faster access time, write without a required erase, single-bit alterability, low-power operation, and in-built OTA upgrade capability. That’s how PCM paves the way for a new generation of zone and domain ECU architectures for automotive applications.

>> This article was originally published on our sister site, EDN.


Sachin Gupta is principal market development engineer in Automotive and Discrete Group (ADG) at STMicroelectronics.

Related Contents:

For more Embedded, subscribe to Embedded’s weekly email newsletter.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.