Texas Instruments Incorporated (TI) and Continental have collaborated on what the companies claim is the first 65 nm ARM Cortex safety microcontrollers with Flash technology in volume production. The Continental processor for advanced control in electronic braking systems (PACE) is the foundation for the Continental MK 100 family of electronic stability control (ESC) systems. This 65 nm Flash technology also serves as the foundation for TI’s Hercules safety MCU open market products. The Continental MK 100 ESC systems boast a high level of safety integration and Continental proprietary safety MCU architecture with TI’s 65nm embedded Flash.
- Smaller form factor, more storage space in vehicles: Integrated MK 100 ESC sensors on the circuit board of the controller and future generations of the electric parking brake will be integrated, controlling Continental or third-party actuators, requiring no separate controller. This integration reduces the amount of controllers, increasing storage space in vehicles.
- Modular approach with a wide range of functions: The MK 100 family can be scaled to suit varying functionalities (e.g., active rollover protection, trailer stability assist, hill start assist) and level of performance the vehicle manufacturer requires (from high-end to entry-level models). This is enabled with the modular scalable design of the safety MCUs that allow variation in performance and functionality seamlessly.
- Improved cost/performance ratio: These safety MCUs offer 65 nm performance with embedded Flash technology on a single chip at great value, allowing for the improved safety features in mass production.
- Enhanced safety architecture and features: These safety MCUs follow a development flow and an architecture aligned with ISO 26262 and IEC61508 standards for easy integration into systems needing safety. The safety MCUs provide a high level of built-in safety for better performance and memory utilization and online diagnostics with dual ARM Cortex-cores in lockstep that are isolated; real-time core comparison, memory protection for the CPU and other bus masters; error correction code (ECC) for Flash and RAM with a single-bit error correction and double-bit error detection (SECDED); RAM optional CPU built-in self-test (BIST) for detection of potential latent faults; self-test capability on core- compare module; intelligent error-signaling module for action based on safety error, parity or optional ECC on peripheral RAMs, redundant timers, as well as continuous voltage and clock monitoring.