Perhaps sensing an opportunity in the low to medium end of the network router and switch market previously served by the now defunct MIPS Technologies, Texas Instruments is rolling out what it calls “purpose-built severs” based on its Keystone multiprocessor chips.
The Keystone chips use a mix of ARM Cortex A15 and TI C66x DSPs along with TI security and networking blocks. TI hopes to win sockets in systems designed to handle media processing, video analytics, industrial imaging and control and other high performance computing jobs suitable for its DSPs.
The first time it has gone after routers and switches in a focused way, TI will be facing a broad set of competitors including Cavium, which uses an architecture based on the MIPS design, Freescale with its mix of Power and ARM based network devices and LSI which is creating SoCs with ARM cores and its own homegrown accelerators.
TI will be differentiating its parts depending on speed and memory. It uses a 256-bit interface from the cores to the SoC clocked at the full 1.4 GHz data rate of the cores. Several vendors use 128-bit interfaces clocked at a third to half the core rate.
In addition, as much as 18 Mbytes of aggregate memory will be used on its high-end Keystone-based SoCs. The company claims it is also unique in supporting 1 and 10 Gbit Ethernet MACs in its chips.
The new Keystone chips sample in December in versions consuming from 6 to 13W. High-end versions will use up to four A15s and six C66x DSPs to deliver up to 352 GMACs and 19,600 Dhrystone MIPS.
Two of the chips will use just one DSP core for workloads with less heavy signal-crunching requirements, while the low-end parts will not contain any DSPs and will focus on applications such as networking and industrial sensor nets.
With pricing starting in the $30 per unit in thousand unit quantities for 850 MHz members of the new family, samples are available now, with volume production by June at the latest.