An unhappy reality of our business is that we’ll surely spend lots of time—far too much time—debugging both hardware and firmware. For better or worse, debugging consumes project-months with reckless abandon. It’s usually a prime cause of schedule collapse, disgruntled team members, and excess stomach acid.
Yet debugging will never go away. Practicing even the very best design techniques will never eliminate mistakes. No one is smart enough to anticipate every nuance and implication of each design decision on even a simple little 4k 8051 product; when complexity soars to hundreds of thousands of lines of code coupled to complex custom ASICs we can only be sure that bugs will multiply like rabbits.
We know, then, up front when making basic design decisions that in weeks or months our grand scheme will go from paper scribbles to hardware and software ready for testing. It behooves us to be quite careful with those initial choices we make, to be sure that the resulting design isn’t an undebuggable mess.
Test Points Galore
Always remember that, whether you’re working on hardware or firmware problems, the oscilloscope is one of the most useful of all debugging tools. A scope gives instant insight into difficult code issues such as operation of I/O ports, ISR sequencing, and performance problems.
Yet it’s tough to probe modern surface-mount designs. Those tiny whisker-thin pins are hard enough to see, let alone probe. Drink a bit of coffee and you’ll dither the scope connection across three or four pins.
The most difficult connection problem of all is getting a good ground. With speeds rocketing toward infinity the scope will show garbage without a short, well-connected ground, yet this is almost impossible when the IC’s pin is finer than a spiderweb.
So, when laying out the PCB add lots of ground points scattered all over the board. You might configure these to accept a formal test point. Or, simply put holes on the board, holes connected to the ground plane and sized to accept a resistor lead.
Before starting your tests, solder resistors into each hole and cut off the resistor itself, leaving just a half-inch stub of stiff wire protruding from the board. Hook the scope’s oversized ground clip lead to the nearest convenient stub.
Figure on adding test points for the firmware as well. For example, the easiest way to measure the execution time of a short routine is to toggle a bit up for the duration of the function. If possible, add a couple of parallel I/O bits just in case you need to instrument the code.
Add test points for the critical signals you know will be a problem. For example:
• Boot loads are always a problem with downloadable devices (Flash, ROM-loaded FPGAs, etc.). Put test points on the critical load signals, as you’ll surely wrestle with these a bit.
• The basic system timing signals all need test points: read, write, maybe wait, clock, and perhaps CPU status outputs. All system timing is referenced to these, so you’ll surely leave probes connected to those signals for days on end.
• Using a watchdog timer? Always put a test point on the time-out signal. Better, use an LED on a latch. You’ve got to know when the watchdog goes off, as this indicates a serious problem. Similarly, add a jumper to disable the watchdog, as you’ll surely want it off when working on the code.
• With complex power-management strategies, it’s a good idea to put test points on the reset pin, battery signals, and the like.
When using PLDs and FPGAs, remember that these devices incorporate all of the evils of embedded systems with none of the remedies we normally use: the entire design, perhaps consisting of tens of thousands of gates, is buried behind a few tens of pins.
There’s no good way to get “inside the box” and see what happens. Some of these devices do support a bit of limited debugging using a serial connection to a pseudo-debug port. In such a case, by all means add the standard connector to your PCB! Your design will not work right off the bat; take advantage of any opportunity to get visibility into the part.
Also plan to dedicate a pin or two in each FPGA/PLD for debugging. Bring the pins to test points. You can always change the logic inside the part to route critical signal to these test points, giving you some limited ability to view the device’s operation.
Similarly, if the CPU has a BDM or JTAG debugging interface, put a BDM/JTAG connector on the PCB, even if you’re using the very best emulators. For almost zero cost you may save the project when/if the ICE gives trouble.
Very small systems often just don’t have room for a handful of test points. The cost of extra holes on ultra-cheap products might be prohibitive. I always like to figure on building a real, honest, prototype first, one that might be a bit bigger and more expensive than the production version. The cost of doing an extra PCB revision (typically $1000 to $2000 for 5-day turnaround) is vanishingly small compared to your salary!
When management screams about the cost of test points and extra connectors, remember that you do not have to load these components during the production run. Install them on the prototypes, leaving them off the bill of materials. Years later, when the production folks wonder about all of the extra holes, you can knowingly smile and remember how they once saved your butt.
When I was a young technician, my associates and I arrogantly believed we could build anything with enough 10k resistors and duct tape. Now it seems that even simple electronic toys use several million transistors encased in tiny SMT packages with hundreds of hairlike leads; no one talks about discrete components anymore.
Yet no matter how digital our embedded designs get, we can never avoid certain fundamental electrical properties of our circuits.
For example, somehow the digital age has an ever-increasing need for resistors—so many, in fact, that most “discrete” resistors are now usually implemented in a monolithic structure, like an SIP, not so different from the ICs they are tied to.
Too often we spend our time carefully analyzing the best way to use a modern miracle of integration only to casually select discrete components because they are, well, boring.
Who can get worked up over the lowly carbon resistor? You can’t even buy them one at a time any more. At Radio Shack they come paired in bright decorator packages for an outrageous sum.
Back when I was in the emulator business we dealt with a lot of user target systems that, because of poor resistor choices, drove the tools out of their minds.
Consider one typical example: a unit based on an 8-MHz 80188, memory and I/O all connected in a carefully thought-out manner. Power and ground distribution were well planned; noise levels were satisfyingly low. And yet, the only tool that seemed to work for debugging code was a logic analyzer. Every emulator the poor designer tested failed to run the code properly. Even a ROM emulator gave erratic results.
Though the emulator wouldn’t run the user’s code, it did show an immediate service of the non-maskable interrupt—which wasn’t used in the system.
(Note: When things get weird, always turn to your emulator’s trace feature, which will capture weirdness like no other tool.)
A little further investigation revealed that the NMI input (which is active high on the188) was tied low through a 47k resistor. Now, the system ran fine with a ROM and processor on the board.
I suppose the 47kpull-down was at least technically legitimate. A few microamps of leakage current out of the input pin through 47k yields a nice legal logic zero. Yet this 47k was too much resistance when any sort of tool was installed, because of the inevitable increase in leakage current.
Was the design correct because it violated none of Intel’s design specs? I maintain that the specs are just the starting point of good design practice. Never, ever, violate one. Never, ever, assume that simply meeting spec is adequate.
A design is correct only if it reliably satisfies all intended applications—including the first of all applications, debugging hardware and software. If something that is technically correct prevents proper debugging, then there is surely a problem.
Pull-down resistors are often a source of trouble. It’s practically impossible to pull down an LS input (leakage is so high the resistor value must be frighteningly low). Though CMOS inputs leak very little, you must be aware of every potential application of the circuit, including that of plugging tools in. The solution is to avoid pull-downs wherever possible.
In the case of a critical edge-triggered (read “really noise sensitive”) input such as NMI, you simply should never pull it low. Tie it to ground. Otherwise, switching noise may get coupled into the input. Even worse, every time you lay out the PC board, the magnitude of the noise problem can change as the tracks move around the board.
Be conservative in your designs, especially when a conservative approach has no downside. If any input must be zero all of the time, simply tie it to ground and never again worry about it. I think folks are so used to adding pull-ups all over their boards that they design in pull-downs through the force of habit.
Once in a while the logic may indeed need a pull-down to deal with unusual I/O bits. Try to come up with a better design.
(The only exception is when you plan to use automatic test equipment to diagnose board faults. ATE gear injects signals into each node, so you’ll often need to use a resistor pull-down in place of a ground. Use a small—really small, like 220ohms—value. )
Though pull-downs are always problematic, well-designed boards use plenty of pull-up resistors—some to bias unused inputs, others to deal with signals and busses that tristate, and some to put switches and other inputs into known one states.
The biggest problem with pull-ups is using values that are too low. A 100k pull-up will in fact bias that CMOS gate properly, but creates a circuit with terribly high impedance.
Why not change to 10k? You buy an order of magnitude improvement in impedance and noise immunity, yet typically use no additional current since the gate requires only microamps of bias.
Vcc from a decent power supply is essentially a low-impedance connection to ground. Connect a 100k pull-up to a CMOS gate and the input is 100k away from ground, power, and everything else—you can overcome a 100k resistance by touching the net with a finger. A 10k resistor will overpower any sort of leakage created by fingers, humidity, and other effects.
Besides, that low-impedance connection will maintain a proper state no matter what tools you use. In the case of NMI from the example above, the tools weakly pulled NMI high so they could run stand-alone (without the target); the 47k resistor was too high a value to overcome this slight amount of bias.
If you are pulling up a signal from off-board, by all means use a very low value of resistance. The pull-up can act as a termination as well as a provider of a logic one, but the characteristic impedance of any cable is usually on the order of hundreds of ohms.
A 100k pull-up is just too high to provide any sort of termination, leaving the input subject to cross coupling and noise from other sources. A 1k resistor will help eliminate transients and crosstalk.
Remember that you may not have a good idea what the capacitance of the wiring and other connections will be. A strong pull-up will reduce capacitive time constant effects.
Once upon a time, back before CMOS logic was so prevalent, you could often leave unused inputs dangling unconnected and reasonably expect to get a logic one. Still, engineers are a conservative lot, and most were careful to tie these spare pins to logic one or zero conditions.
But what exactly is a logic one? With 74LS logic it’s unwise to use Vcc as an input to any gate. Most LS devices will happily tolerate up to 7 volts on Vcc before something fails, while the input pins have an absolute maximum rating of around 5.5 volts.
Connecting an input to Vcc creates a circuit where small power glitches that the devices can tolerate may blow input transistors. It’s far better (when using LS) to connect the input to Vcc through a resistor, thus limiting input current and yielding a more power-tolerant design.
Modern CMOS logic in most of its guises has the same absolute maximum rating force as for the inputs, so it’s perfectly reasonable to connect input pins directly tock—if you’re sure that production will never substitute an LS equivalent for the device you’ve called out.
CMOS does require that every unused input be pulled to a valid logic zero or one to avoid generating an SCR latchup condition. Fast CMOS logic (like 74FCT) switches so quickly, even at very low clock rates, that glitches with Fourier components into billions of cycles per second are not uncommon. Reduce noise susceptibility by tying your logic zeroes and ones directly tithe power and ground planes.
And yet, one must balance the rules of good design with practical ways to make debuggable system. A thousand years ago circuits used vacuum tubes mounted on a metal chassis. All connections were made by point-to-point wiring, so making engineering changes during prototype checkout must have been pretty easy.
Later, transistors and ICs lived on PC boards, but incorporating modifications was still pretty simple. Now we’re faced with whisker-thin leads on surface-mount components, with8- and 10-layer boards where most tracks are buried under layers of epoxy and out of reach of our X-Acto knives.
If we tie every unused input, even on our spare gates, to a solid power or ground connection, it’ll be awfully hard to cut the connection free to tie it somewhere else. Lifting the pins on those spare gates might be a nightmare.
One solution is to build the prototype boards a little differently than the production versions. I look at a design and try to identify areas most likely to require cutting and pasting during checkout.
A prime example is the programmable device—PALs orFPGAs or whatever. Bitter experience has taught me that probably I’ll forget a crucial input to that PAL, or that I’ll need to generate some nastily complex waveform using a spare output on the FPGA.
Some engineers figure that if they socket the programmable logic, they can lift pins and tack wires to the dangling input or output. I hate this solution. Sometimes it takes an embarrassing number of tries to get a complex PAL right—each time you must remove the device, bend the leads back to program it, and then reinstall the mods. (An alternative is to put a socket in the socket and lift the upper socket’s leads. )
When the device is PLCC or another, non-DIP package, it’s even harder to get access tithe pins. So I leave all unused inputs on these devices unconnected when building the prototype, unfortunately creating a window of vulnerability to SCR latchup conditions.
Then it’s easy to connect mod wires to the unconnected pins. When the first prototype is done I’ll change the schematic to properly tie off the unused inputs so prototype 2 (or the production unit) is designed correctly.
In years of doing this I have never suffered a problem from SCR latchup due to these dangling pins. The risk is always there, lurking and waiting for an unusual ESD or perhaps even a careless ungrounded finger biasing an input.
I do tie spare gate inputs to ground, even with the first run of boards. It just feels a little too dangerous to leave an unconnected 74HC74 lead dangling. However, if at all possible, I have the person doing the PCB layout connect these grounds on the bottom layer so that a few quick strokes of the X-Acto knife can free them to solve another “whoops.”
In designs that use through-hole parts, by all means leave just a little extra room around each chip so you can socket the parts on the prototype. It’s a lot easier to pull a connected pin from a socket than to cut it free from the board.
For a number of years embedded systems lived in a wonderful era of compatibility. Just about all the signals on any logic board were relatively slow and generally TTL compatible. This lulled designers into a feeling of security, until far too many of us started throwing digital ICs together without considering their electrical characteristics.
If a one is 2.4 volts and a zero 0.7, if we obey simple fanout rules, and as long as speeds are under 10MHz or so, this casual design philosophy works pretty well. Unfortunately, today’s systems are not so benign.
In fact, few microprocessors have ever exclusively used TTL levels. Surprise! Pull out a data sheet on virtually any microprocessor and look at the electrical specs page—you know, the section without coffee spills or solder stains. Skip over those 300 tattered pages about programming internal peripherals, bypass the pizza-smeared pinout section, and really look at those one or two pristine pages of DC specifications.
Most CPUs accept TTL-level data and control inputs. Few are happy with TTL on the clock and/or reset inputs. Each chip has different requirements, but in a quick look through the data books I came up with the following:
• 8086: Minimum Vih on clock: Vcc – 0.8
• 386: Minimum Vih on clock: Vcc – 0.8 at 20 MHz, 3.7 volts at 25 and 33MHz
• Z80: Minimum Vih on clock: Vcc – 0.6
• 8051: Minimum Vih on clock and reset: 2.5 volts
In other words, connect your clock and maybe reset input to a normal TTL driver, and the CPU is out of spec. The really bad news is that these chips are manufactured to behave far better than the specs, so often they’ll run fine despite illegal inputs. If only they failed immediately on any violation of specifications! Then, we’d find these elusive problems in the lab, long before shipping a thousand units into the field.
Fully 75% of the systems I see that use a clock oscillator (rather than a crystal) violate the clock minimum high-voltage requirement. It’s scary to think we’re building a civilization around embedded systems that, well, may be largely misdesigned.
If you drive your processor’s clock with the output of a gate or flip-flop, be sure to use a device with true CMOS voltage levels. 74HCT or 74ACT/FCT is good choices. Don’t even consider using 74LS without at least a heavy-duty pull-up resistor.
Those little 14-pins silver cans containing a complete oscillator are a good choice – if you read the data sheet first. Many provide TTL levels only. I’m not trying to be alarmist here, but look in the latest DigiKey catalog—they sell dozens of varieties of CMOS and TTL parts.
Clocks must be clean. Noise will cause all sorts of grief on this most important signal. It’s natural to want to use a The venin termination to more or less match impedance on a clock routed over a long PCB trace or even off board. Beware! The venin terminations (typically a 220-ohm resistor to +5 and a 270 to ground) will convert your carefully crafted CMOS level to TTL.
Use series damping resistors to reduce the edge rate if noise is a problem. A pull-up might help with impedance matching if the power supply has a low impedance (as it should).
A better solution is to use clock-shaping logic near the processor itself. If the clock is generated a long way away, use a CMOS hysteresis circuit (such as a 74HCT14) to clean it up. The extra logic adds delay, though. If your system requires clock synchronization, then use a special low-skew clock driver made for that purpose.
In slower systems—under 20MHz or so—I prefer to design circuits that don’t depend on a synchronous clock. What happens if you change to a second sourced processor with slightly different timing? Keep lots of margin.
Never drive a critical signal such as clock off board without buffering. There are a very few absolutely critical signals in any system that must be noise-free. Examine your design and determine what these are, and take appropriate steps. Clock, of course, is the first that comes to mind. Another is ALE (Address Latch Enable), used on processors with a multiplexed address/data bus. A tiny bit of noise on ALE can cause your address register to latch in the middle of a data cycle, driving an incorrect address to the memories.
OK—so now your voltage levels are right. Go back to the data sheet and make sure the clock’s timing is in spec. The 8088 requires a 33% clock duty cycle. Sure, it’s a little odd, but this is a fundamental rule of nature to 8088 designers. Other chips have tight duty cycle requirements as well.
Rise and fall times are just as important, though difficult to design for. Some chips have minimum rise/fall time requirements! It’s awfully hard to predict the rise/fall time for a track routed all over the board. That’s one attraction of microprocessors with a clock-out signal. Provide a decent clock-input to the chip, connect nothing to this line other than the processor, and then drive clock-out all over the board.
Motorola’s 68HC16 pulls a really neat trick. You can use a 32,768-Hz standard watch crystal to clock the device. An internal PLL multiplies this to 16MHz or whatever, and drives a clock output to feed to the rest of the board. This gets around many of the clock problems and gives a “free” accurate time-of-day clock source.
The processor’s reset input is another source of trouble. Like clocks, some processors have unusual input voltage requirements for reset. Be wary.
Other chips require synchronous circuits. The old Z280 had a very odd timing spec, clearly spelled out in the documentation, that everyone ignored only to find massive troubles getting the CPU to start. I think every single Z280 design in the world suffered from this particular ill at one time or another.
Sometimes slew rate is an issue. The old RC startup circuit generates a long ramp that some processors cannot tolerate. You might want to feed it into a circuit with hysteresis, like a Schmidt Trigger, to clean up the ramp.
The more complex CPUs require a long time after power-up to stabilize their internal logic. Reset cannot be unasserted until this interval goes by. Further complicating this is the ramp-up time of the system power supply, as the CPU will not start its power-up sequence until the supply is at some predefined level. The 386, for example, requires 219clock cycles if the self-test is initiated before it is ready to run.
Think about it: in a 386 system four events are happening at once. The power supply is coming up. The CPU is starting its internal power-up sequence. The clock chip is still stabilizing. The reset circuit is getting ready to unassert reset. How do you guarantee that everything happens to spec?
The solution is a long time delay on reset, using a circuit that doesn’t start timing out until the power supply is stable. Motorola, Dallas, and others sell wonderful little reset devices that clamp until the supply hits 4.5 volts or so. Use these in conjunction with a long time constant so the processor, power supply, and clocks are all stable before reset is released.
When Intel released the 188XL they subtly changed the timing requirements of reset from that of the 188. Many embedded systems didn’t function with this “compatible” part simply because they weren’t compliant with the new chip’s reset spec. The easy solution is a three-pin reset clamp.
The moral? Always read the data sheets. Don’t skip over the electrical specifications with a mighty yawn. Those details make the difference between a reliable production product and a life of chasing mysterious failures.
One of my favorite bumper stickers reads “Question Authority.” It’s a noble sentiment in almost all phases of life – but not in designing embedded systems. Obey the specifications listed in the chip vendors’ datasheets!
If you’ve read many annual reports from publicly held companies, you know that the real meat of their condition is contained in the notes. This is just as true in a chip’s datasheet. It seems no one specifies sink and source current for a microprocessor’s output, but the specification of the device’s Vol and Voh will always reference a note that gives the test condition. This is generally a safe maximum rating.
With watchdog timers and other circuits connected to reset inputs, be wary of small timing spikes. I spent several frustrating days working with an AMD part that sometimes powered up oddly, running most instructions fine but crashing on others. The culprit was a sub nanosecond spike on the reset input, one too fast to see on a 100-MHz scope.
Homemade battery-backed-up SRAM circuits often contain reset-related design flaws. The battery should take over, maintaining a small bias to the RAM’s Vcc pins, when main power fails. That’s not enough to avoid corrupting the memory’s contents, though.
As power starts to ramp down, the processor may run crazy for a while, possibly creating errant writes that destroy vast amounts of carefully preserved data in the RAM. The solution is to clamp the chip’s reset input as soon as power falls below the part’s minimum Vcc (typically 4.75 volts on a 5-volt part).
With reset properly asserted, Vcc now at zero, and the battery providing a bit of RAM support, be sure that the chip select and write lines to the RAM are in guaranteed “idle” states. You may have to use a small pull-up resistor tied to the battery, but be wary of discharging the battery through the resistor when the system is operating normally.
And be sure you can actually pull the line up despite the fact that the driver will experience Vcc’s from +5 to zero as power fails. The cleanest solution is to avoid the problem entirely by using a RAM with an active high chip select, which you clamp to zero as soon as Vcc falls out of spec.
Despite our apparent digital world, the harsh reality is that every component we use pushes electrons around. Electrical specifications are every bit as important to us as to an analog designer.
This field is still electronic engineering filled with all of the tradeoffs associated with building things electronic. Ignore those who would have you believe that designing an embedded system is nothing more than slapping logic blocks together.
Next, in Part 2 : “Small CPUs, watchdog times and making PCBs.“com