Tips on using CPLDs to reduce system processor power consumption -

Tips on using CPLDs to reduce system processor power consumption

One of the most critical factors in designing portable electronicstoday is reducing overall system power consumption. With increasedconsumer expectations, portable devices require longer battery life andhigher performance. Even power reductions on the order of 10mW arecrucial to portable system designers and manufacturers.

Designers use several design techniques to significantly reduceoverall system power consumption, such as:

* Reducing operating voltage;
* Optimizing system and CPU clock frequency;
* Eliminating spikes of large current consumption during the power upsequence;
* Efficiently managing system battery operation;
* Efficiently managing operating mode of system devices;
* Minimizing bus activity;
* Reducing bus capacitance;
* Reducing switching noise.

These are just a few examples of design techniques for reducingthepower consumption in any end application. One of the most importantpower-saving techniques mentioned in the list is the ability to managethe operating mode of devices in the system.

Many manufacturers today offer devices with power saving modes thattemporarily suspend the device from its normal operation. These deviceshave the option to power down or transition to a non-functioning stateif the device is not active for a specific amount of time.

This feature is available on many of today's microprocessors andMCUs. By taking advantage and managing the operating mode of largepower consumers on a PCB, such as the processor, the overall powerconsumption of the system can be reduced significantly.

Reducing power consumption involves correct management of theoperating mode of a device and designing a system to take advantage ofthe modes a device can operate within.

Offloading operations of the microprocessor allows it to stay in itslow-power state for a longer amount of time. One way to reduce systempower is to allow a low-power PLD, such as a CPLD, to manage theseoffloaded operations.

This article describes this possibility, along with types ofoperations that allow a processor to remain in a low-power statelonger, thereby reducing system power consumption.

Figure1: Shown is the typical power consumption of system components in a WebPad application.

Microprocessor modes
In some portable applications, the CPU can consume 30 percent of theoverall system power. Figure 1 above illustrates the typical power consumption of system components in a WebPad application.

Microprocessor power consumption can range from 720µW to 1Wduring normal operation. Microprocessor operating modes vary by partand manufacturer and include modes such as normal; run, sleep, suspend,standby, stop and idle operation.

Operating modes can vary in power consumption as much as 230mWbetween states. Normal operation of some low-power microprocessors canbe as little as 250mW.

Figure 2 below illustratesthe power consumption of the Intel StrongARM SA-1110 microprocessoroperating modes. The power dissipation numbers shown in Figure 2 aredetermined by operating at 206MHz with a nominal external voltagesupply of 3.3V and internal voltage supply of 1.8V.

Figure2: Shown is the difference in power consumption of operating modes in amicroprocessor.

Operating modes of the StrongARM processor include normal, idle andsleep. In normal operation, the CPU is full-on, with the device fullypowered and receiving active clocks.

In idle mode, even though power is applied to the CPU and othercomponents, all clocks to the CPU are stopped, with only clocks toperipheral devices active. In sleep mode, power to the CPU and otherperipheral components is disabled. Sleep mode disables all functionsexcept the real-time clock, interrupt controller, power manager andgeneral purpose I/O.

Microprocessors with power saving modes have an on-board powermanagement controller. Operating modes allow the OS or softwareapplication to temporarily suspend the CPU. The microprocessor executesa series of instructions to place itself into a power saving state.Once in a power down mode, several components of the microprocessor canstill respond to system interrupts.

Idle and sleep modes
For example, the idle mode of the StrongARM SA-1110 processor savessignificant power, but certain modules remain powered, such as the LCD,memory and I/O controllers. Even though the clock to the CPU isstopped, peripheral modules are still active.

The idle mode can still consume a significant amount of power, onthe order of 100mW. By placing the processor into the sleep mode, onlyactive modules are powered to respond to interrupts and wake up signalrequests.

Sleep mode consumes even less power than idle mode; currentconsumption can be less than 100mA. For a microprocessor to return tonormal operation from a power down mode, an event must occur.

The following events can wake up the processor, but vary based onmanufacturer, part, and current operating mode:

* Hardware reset;
* System interrupt;
* GPIO interrupt;
* Real-time clock interrupt;* OS timer interrupt;
* Peripheral interrupt;
* External wake-up signal.

Upon recognition of an enabled wakeup event, the microprocessor willbegin a series of steps to wake up from a power down state. Figure 3 below illustrates thegeneral flow for a processor waking up from a power down mode.

Figure3: Shown is the general flow for a processor waking up from a powerdown mode

CPLD design
Operating modes are using when the microprocessor is idle for aspecific amount of time. When a microprocessor receives an enabledinterrupt, the processor will respond to the interrupt request.

When the processor is responding to the interrupt, it will operatein its run or normal mode. Reducing the number of interrupts to theprocessor will increase the time the processor is in a power savingstate. Ideally, if the microprocessor does not have any instructions toexecute, it will remain in a power saving mode forever.

Figure4: Using an external data acquisition device to offload interruptrequests required of the microprocessor will reduce overall systempower.

Inserting an external device to respond and handle system interruptscan reduce the operations required of the processor. By allowing themicroprocessor to stay in its power down mode as long as possible,significant power savings can be realized.

Using a low-power PLD to supplement the microprocessor will savesystem power and increase system battery life. The industry's latestCPLD offerings simultaneously deliver high performance and low powerconsumption.

Standby current of a typical low-power CPLD is less than100µA. Figure 4 above illustrates using a reprogrammable CPLD to interface to incoming systeminterrupts. Using an external data acquisition device to offloadinterrupt requests required of the microprocessor will reduce overallsystem power.

System interrupts
Depending on the end application for the processor, a variety ofexternal devices may interrupt the processor. These interrupts includeboth data acquisition and data processing requests.

By separating data processing interrupts to the microprocessor, dataacquisition interrupts can now be serviced by the external CPLD.Utilizing a CPLD to handle data acquisition interrupts will offloadinterrupt requests to the microprocessor and save power.

Categorization of the type of data acquisition interrupts to theCPLD will depend on the end application. Peripheral devices or incomingdata demanding a response to incoming data can be classified as dataacquisition interrupt requests. Data acquisition interrupts include:

* Memory access interrupts;
* Communication interfaces such as I2C, UART, SPI or ISA;
* GPIO interrupts;
* LCD interface interrupts.

This is not a complete list of interrupts that can be processed bythe CPLD, but provides a starting point for the system design.

Operational flow
Figure 5 below illustrates themain operational flow for the design of a CPLD. Once a valid externalinterrupt is recognized by the CPLD, it will determine if it containsthe functionality to process the interrupt.

Once the CPLD has processed the interrupt, it can assert aninterrupt to the processor for any data processing requests needed. Ifthe CPLD is unable to process the interrupt, the interrupt is passed tothe processor. The CPLD also monitors the operating state of theprocessor.

Figure5: Shown is the main operational flow for the design of a CPLD

The low-power CPLD design consists of an interrupt interface andcontroller to handle interrupt requests, the functionality to processthe interrupt, and a processor interface. The main functions of theCPLD are as follows:

Interruptinterface. The interrupt interface of the CPLD receives allexternal device interrupt requests previously recognized by themicroprocessor. The interrupt interface determines if the CPLD iscapable of processing the interrupt request. The CPLD handles dataacquisition interrupts that request data receiving and storagecapabilities.

If the CPLD is unable to process the interrupt, the interrupt ispassed to the microprocessor. The CPLD interrupt interface provides themasking capability for all interrupt sources and the ability todetermine the interrupt source.

Programmable logic provides flexibility to change the trigger mode,which includes a high or low level and falling or rising edgesensitivity. The CPLD interrupt control registers are similar to theregisters in the microprocessor.

Interruptcontroller. The CPLD interrupt controller emulates thefunctionality that exists in the system microprocessor. The interruptcontroller interprets from which device the data acquisition interruptwas received and initiates the processing of the interrupt.

The CPLD processes the data acquisition interrupt request that wouldhave otherwise interrupted the microprocessor. The interrupt controllerinitiates the action to process the request. An example of this is anapplication where the CPLD is receiving data from a remote device.

The device is requesting to write the data being sent into memory.The CPLD interrupt controller recognizes a valid interrupt andinitiates the memory interface to interpret the data. Peripheral deviceinterfaces—The CPLD provides the interface to system devices that areneeded in processing interrupt requests. Device interfaces that areneeded are dependent on the end application.

When an external device interrupts the CPLD to read or write datainto a memory component, that particular memory interface is needed inthe CPLD design. The types of interfaces needed can range from memoriesto LCD interfaces to communication interfaces such as PCI, UART, SPIand ISA.

Microprocessorinterrupt interface. The CPLD, like any external devicerequesting services of the processor, has the capability to interruptthe microprocessor.

The CPLD must be able to interrupt the microprocessor once a dataacquisition operation is complete. The designer has the option to setthe priority level of interrupt requests from the CPLD and whether ornot interrupts received from the CPLD will wake the processor from apower down state.

Microprocessoroperating mode interface. Depending on the systemmicroprocessor, the CPLD will be able to recognize the operation stateof the processor. Some microprocessors provide external pins thatrepresent the current operating mode.

Depending on the CPLD and microprocessor design, the CPLD couldrecognize the current operating state of the processor and determinewhether to assert an interrupt to the processor to execute a waitinginterrupt.

For example, if a low priority interrupt is received by the CPLD andthe processor does not need to transition from its low-power state, theCPLD can create a register indicating pending interrupts. Then when theprocessor wakes, the interrupt pending register can be read by themicroprocessor.

Figure 6 below  illustrates the power savings that may be realized in a typical batteryoperated device using a leading-edge, low-power CPLD (left) vs. astandalone microprocessor design. The power requirements of the CPLDare minimal compared with the power savings realized by keeping themicroprocessor in its low-power modes for a longer amount of time.

Standby current of a typical low-power CPLD is on the order of100µA. The operating power consumption depends on the applicationand clock frequency.

Figure6: Shown is the power savings that may be realized in a typical batteryoperated device using a leading-edge, low-power CPLD (left) vs. astandalone microprocessor design (right).

For a 64-macrocell CPLD fully populated with 16bit counters and a50MHz clock, ICC is around 10mA. Note that the actual power savingsrealized will depend on the system design, including the type ofmicroprocessor and the CPLD design.

Along with power savings attained using a CPLD, interrupt responsetime is reduced. The peripheral device no longer has to wait the delaytime for the microprocessor to wake from a power saving state.

Additional design savings that can be realized include:

* Reducing the number of interruptions to the processor;
* Reducing the number of processor wake-up cycles over a length oftime;
* Reduction of clock frequency without impact on throughput;
* Running the processor at a lower frequency for data processingoperations;
* Running the CPLD at a higher frequency for data acquisitionoperations.

Designing a power-sensitive application involves not only usingsoftware for power management, but utilization of hardware designtechniques. Designing a low-power CPLD to keep a microprocessor in alow-power operating state longer can significantly reduce system powerconsumption.

Mark Ng is an ApplicationsEngineer at Xilinx Inc.

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