In “TLM+ Modeling of Embedded HW/SW Systems , ” Wolfgang Ecker with Volkan Esen Robert Schwencker Thomas Steininger and Michael Velten of Infineon Technologies AG analyze the limitations imposed on Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) due to the growing complexity of SoC architectures.
To overcome the bottlenecks in full hardware/software simulation they describe a new TLM based modeling system they call TLM+ that allows for further abstraction beyond the currently applied TLM methodology.
It enables a higher modeling abstraction through merging hardware dependent driver software at the lowest level with the HW interface. Thus, sequences of HW transactions can be merged to single HW/SW transactions while preserving both the HW architecture and the low-level to high-level SW interfaces.
In order to maintain the ability to validate timing-critical paths, they have developed a new resource model concept is introduced which compensates the loss of timing information, induced by merging HW transactions. Experimental results show a speed show a speed-up of up to 1000x at a timing error of approximately 10%.