ESPOO, Finland Version 7.92 of APLAC Solutions' circuit design and analysis tool, which combines RF-IC and analog simulation with a range of functions for analysis and optimization, adds enhanced measurement support for mixers, amplifiers and oscillators.
Measurement support can be ordered to handle repetitive simulation tasks, enabling the designer to manage a larger-scale simulation with more focus and capacity. The model-order reduction analysis method is implemented for faster analysis of linear circuits.
The latest APLAC enhanced technologies include new WLAN system blocks, BSIM4 v4.30 and MOS11 as well as a new PinDiode model.
The power and efficiency of electronic design can be improved by integrating the APLAC Simulator with design frameworks such as Cadence Virtuoso and Mentor Graphics Design Architect, RF Architect, and PowerLogic.
The company says that APLAC has been used in designing over 30% of all mobile phone RFIC circuits. Other applications of the software are also found in MEMS and acoustic design.