MADISON, Wis. — Designing a complex SoC by mixing and matching different semiconductor IP cores is hard enough. The job gets tougher, with higher costs and arduous process of the validation and verification, after the SoC comes back from a fab, according to Rupert Baines, CEO of UltraSoC.
To address such post-silicon woes, UltraSoC, a Cambridge, U.K.-based supplier of advanced debugging and analytic technology for embedded systems, is claiming that it has devised for SoC designers “a complete integrated development environment that combines comprehensive debug, run control, and performance tuning.”
By leveraging technologies from Imperas and Percepio, UltraSoC updated its debugging toolset, now called UltraDevelop 2. It plans to offer “system-level on-chip monitoring and analytics infrastructure” with advanced visualization and machine learning capabilities, according to the company.
Many semiconductor experts blame the rising cost of SoCs on skyrocketing photomask costs. While that’s true, even more worrisome to many semiconductor companies is the expense of verifying and validating an SoC, said Baines.
The crux of the issue is “systemic complexity” in SoCs, Baines told us.
The number of semiconductor intellectual property blocks used on a chip is growing by leaps and bounds. More significant is the growing number of interactions among those blocks.
“These sophisticated, complicated blocks integrated on a chip no longer function independently,” said Baines. “Instead of two processors interacting each other in a linear fashion, several blocks are talking among themselves in 10 or more different ways.” These interactions are “exploding,” among a variety of IP blocks including memory controllers, co-processors and accelerators integrated on an SoC, he explained.
Over the last decade, chip designers have transitioned from designing multicore processors to manycore processors and even heterogeneous multicore processors. While this evolution has been painful, Baines said the situation is becoming even more dire because it is not unusual to find an SoC that integrates several different processor architectures — such as cores from Arm, Ceva’s DSP, GPU and RISC-V.
Because each of these processors comes with its own development tools, the consequence is “a vendor silo.”
“Most CPU IP vendors have tools that report on the functionality of their IP,” said Richard Wawrzyniak, principal analyst for ASIC and SoC at Semico Research Corp. “ARM, for example, has their CoreSight product, which is similar to what UltraSoC has, but only works with their own products.”
Under such an environment, Baines noted, a designer who wants to verify on an SoC must look at one screen to see what’s going on inside its Arm cores, while peeking at another screen to see how Ceva’s DSP core is doing. These tools offer no time stamping. In sum, SoC designers have nary one tool to see in a single view what’s going on with an SoC at a system level.
UltraDevelop 2 allows SoC designers to see real-time actionable insights in a single window. In the photo above, a demonstration board containing an Arm CPU generates a fractal pattern on the screen, while the engineer views the operation of the program via the GUI on his workstation. (Photo: UltraSoC)
UltraSoC’s Ultra Develop2 will change that, promised Baines. “SoC designers can see on one screen what’s going on in Arm, Ceva, memory and interconnect. If you halt an Arm core, for example, you can halt the whole system,” he said.
UltraSoC is pitching its newly updated UltraDesign 2 as a tool to display the status of hardware and software of an SoC “in one, coherent view.”
The integrated system-level view isn’t the only thing UltraSoC offers. Semico’s Wawrzyniak noted that UltraSoC’s tool suite “also performs many additional functions like security and fine tuning of the memory controller / memory interaction and fine tuning of power and power management functions.”
Unlike UltraDevelop 1, an initial “demo grade” version, Ultra Develop 2 is “product grade,” noted Baines. More important, his firm made improvements in the new version by integrating third-party tools from Imperas and Percepio.
The inclusion of Imperas Multi-Processor Debugger (MPD), for example, “enables support for today’s multi-core, multi-threaded platforms, including devices that combine cores based on different CPU architectures into complex heterogeneous systems,” according to UltraSoC. The inclusion of Percepio’s Tracealyzer within UltraDevelop 2 brings “data analytics and visualization capabilities” to the UltraDevelop suite, “marrying the worlds of hardware and software development.”
UltraSoC explained that the Tracealyzer tool “understands” the meaning of high-level events within software or an RTOS, connecting related events and views, and complementing the information gathered via UltraSoC’s hardware monitors.