Smartphones, wearables, Internet of Things (IoT) devices and other mobile-connected products are growing more advanced and complicated. Designers and developers find themselves working with more and more peripherals dotted around either a printed circuit board (PCB) or other systems altogether. Systems are more densely packed with sensors and other components, and application processors and/or sensor hubs require more from their interfaces to control and transmit data to/from them.
The MIPI I3C v1.1 interface specification, announced Jan. 15, 2020, links all of these peripherals back to an application processor at higher speeds than previously possible and with greater system controllability, manageability and integrity (Figure 1). Extensible use of extra bus lanes (single, dual or quad) allows I3C v1.1 to reach an effective data rate close to 100 Mbps without requiring additional implementation complexity, cost or development cycles. And a strategically chosen array of new features delivers improvements to overall system reliability and resiliency.
Figure 1. MIPI I3C System Diagram (MIPI Alliance)
I3C v1.1 is ideal for today’s system-level implementers seeking a low-cost, off-the-shelf standardized utility bus solution with small silicon and PCB footprints and a well-defined and readily available ecosystem of peripherals, sensors and applications. Furthermore, it’s a forward-pitched solution for designers and developers. MIPI I3C has been engineered to seamlessly adapt to the next-generation challenges that tomorrow’s IoT devices, smartphones, wearables and other mobile-connected products present.
Evolving Integration Needs
To understand how powerful and perfectly timed the new capabilities in I3C v1.1 are, it is important to look at the development context in which they’ve been defined.
Almost 40 years ago, I2C transformed chip communications. Since the invention of the “Inter-Integrated Circuit” serial computer bus in 1982, virtually all of the world’s chip manufacturers have adopted I2C for short-distance communications. It emerged over the years as a de facto interface to connect low-speed peripherals to processors in electronic systems.
However, in today’s unfolding era of increasingly diverse systems, the limitations of the venerable I2C are evident. It remains a functional resource—but not a totally trusted one in more complex product configurations and as the need for speed has evolved. Designers and developers have grown wary of the actual performance that can be achieved via I2C. They might target operating I2C at 1 MHz, for example, but when implemented in a complex system, the actual speed that can be achieved might be back down to 400 KHz.
2017 brought about another transformation. MIPI I3C was introduced to improve upon the features, performance and power utilization of I²C, while maintaining backward compatibility for most devices. The industries creating IoT devices, smartphones, wearables and other mobile-connected products came together through the MIPI I3C Working Group to create a specification that would further simplify integration of more and more sensors and other peripherals in small, space-constrained form factors. The goal was to address key pain points that many developers were dealing with when working with I2C and other legacy interfaces such as the serial peripheral interface (SPI) (Figure 2).
Figure 2. MIPI I3C vs. I2C FM+ Data Blocks Bit Rates in Mbps (12.5 Mhz Clock) (MIPI Alliance)
Version 1.0 of MIPI I3C established a crucial baseline for the new protocol, and the specification successfully became relied upon in applications such as accelerometers, actuators, haptics feedback, infrared or ultraviolet sensing, near-field communications, time-of-flight cameras, touch screens, transducers and ultrasonic sensors. The newly introduced v1.1 is the first update to build on the MIPI I3C foundation.
Unlocking New Application Spaces
Data transport between hosts and devices can now take place across multiple lanes in all modes of I3C v1.1 (Figure 3), including the new bulk transport mode, HDR-BT. Extending from two to three wires, for example, doubles transport speed, thus reducing the time the host is “awake” and waiting to process data from the device, and thus reducing system power consumption. And dramatic rate increases can be achieved as the implementer sees fit, without necessitating the implemention of more general-purpose input/outputs (GPIOs), more advanced protocols or faster timing. This makes it simple and cost efficient for designers and developers to achieve the speed bump they need, with the tradeoffs they choose, for advanced emerging applications such as “always-on” imaging.
Figure 3. MIPI I3C Multi-Lane Effective Bit Rates, in Mbps (MIPI Alliance)
In addition, v1.1 delivers a variety of key new features—comprehensive flow control, enhanced error detection/recovery, grouped addressing, outsider end transfer, slave reset and improved common command code (CCC) capabilities, among them. Implemented on a standard complementary metal oxide semiconductor (CMOS) I/O and utilizing a simple clock and data(s) interface, MIPI I3C v1.1 enables a host processor to be able to assess what is going on in the different peripherals around either a PCB or system. For example, enhanced system understanding and accountability for heat, performance, integrity, security and other attributes allow a host controller to operate with a better idea of what is going on in the real world of the overall system that it is orchestrating, and these are the kinds of tasks and devices that MIPI I3C was designed to bus together. Whereas legacy interfaces are chosen for particular attributes (perhaps data rate, low pin count and/or built-in bus management) and then linked together over common, higher-level protocols, MIPI I3C was engineered to deliver all such benefits. In this way, systems can migrate toward one new common bus, as opposed to a fragmented collection.
Furthermore, the broad applicability and appeal of the new features rolled out in v1.1 work together to allow I3C to be used in brand new ways. We may see I3C communications inside a system-in-package (SiP) or among different, large systems to fuel use cases such as DIMM5 (SDRAM) memory sideband channel, imaging device control, server system management, debug application communications, touchscreen command and communications, as well as sensor device command, control and data transport.
Moreover, the features in v1.1 render MIPI I3C more likely to be trusted by developers and designers in the critical path of products—and position the interface to keep pace with the bandwidth demands of emerging devices with more sensors and other peripherals, such as 360-degree cameras, smart industrial devices, robots and drones. In IoT edge devices, I3C can help reduce the number of interface pins needed to allow for smaller, lower-cost MCU-package designs. With its higher, more efficient data transport, I3C also can reduce power consumption, which is valuable given that many IoT devices are battery operated and/or net zero energy.
Because so many of the advances that the MIPI I3C Working Group enabled in v1.1—such as a standardized slave reset capability and improved error handling and flow control—were related to the drawbacks and additional work that typically had to be done to get I2C and SPI to function, the development community is now primed for wide-scale migration to I3C. The new version delivers a robust, adaptable and flexible upgrade path from the decades-old legacy interfaces.
Already At Work Anticipating Tomorrow’s Demands
With MIPI I3C, developers and designers in mobile and multiple other markets, including automotive, PC clients, data centers, drones, industrial and the IoT, can take advantage of a well-supported, vibrant and growing ecosystem that is grounded in and committed to interoperability. Industry liaisons are forming to further system manageability and security. For example, the JEDEC Solid State Technology Association collaborated with MIPI in development of the new 1.0v JEDEC Module SidebandBus, a superset of the MIPI I3C Basic bus.
This MIPI I3C ecosystem is the foundation on which the next cycle of innovation in chip and system communications will be set into motion. Companies are encouraged to engage through MIPI Alliance’s interoperability workshops and specification development activities.
So, what’s next for I3C?
The MIPI I3C Working Group is striving to ensure that the specification’s feature set and scope remain relevant. Discussions are already underway about the enhanced capabilities—longer reach, various improvements, automotive requirements, speed increases, new multi-lane uses, standardized connectors and other feature refinements—that the next version of MIPI I3C may demand.
|Ken Foust is Chair of the MIPI I3C Working Group and a Principal Engineer at Intel Corporation.|