Calypto Design Systems Inc. is collaborating with Virage Logic Corp. and the Semiconductor Technology Academic Research Center (STARC) to reduce on-chip SoC power.
Extending its ongoing, independent efforts with STARC and Virage Logic, the multi-technology collaboration resulted in the development of a seamless flow for designs with various functional modes that control multiple on-chip power domains to achieve power savings.
Initial results show up to 50 percent dynamic power reduction and up to 40 percent leakage power reduction in embedded SoC memories using Calypto's PowerPro MG tool and Virage Logic's SiWare memory compilers.
Using Calypto's patented sequential analysis technology, PowerPro MG (for Memory Gating) constructs memory gating logic that works in conjunction with the low-power memory modes in Virage Logic's SiWare Memory compilers to produce a lower power memory implementation.
The SiWare Memory compilers provide several different low power modes – light sleep, deep sleep and shut down to allow designers to reduce leakage power when the memory is not being accessed. The compilers automatically generate PowerPro MG models enabling STARC to easily integrate PowerPro MG into their low power design flow.
“Collaboration, such as this one between Calypto, Virage Logic, and STARC, is the most efficient way to make dramatic methodology improvements that enable our customers to deliver the most advanced, power-efficient designs ahead of their competition,” according to Tom Sandoval, chief executive officer of Calypto.