Tunable down-converter IP core boosts channel density - Embedded.com

Tunable down-converter IP core boosts channel density

Pentek announced an addition to its GateFlow FPGA IP Library that implements a 256-channel narrowband digital down-converter (DDC). Designed for use in Xilinx’s Virtex II, Virtex II Pro, or Virtex 4 FPGAs, the model 4954-430 core utilizes a unique architecture to achieve 64 times the channel capacity of conventional quad ASIC down-converters. This IP core is suited for application developers requiring a high number of digital down-converter channels with size, weight, cost, and power constraints, such as military radios and commercial wireless.

Accepting real or complex data samples at rates up to 185 MHz, the architecture uses a channelizer stage that generates 1024 fixed adjacent frequency channels with alias-free performance greater than 75 dB across each channel's pass band. A 256-output switch matrix follows the channelizer, providing a coarse tuning capability for the desired output channels.

Each of the 256 DDCs has a programmable numerically controlled oscillator (NCO) to implement independent fine-tuning for each channel and mixer to translate the signal of interest to baseband. A decimating FIR low-pass filter then defines the channel bandwidth of the baseband output. The NCOs have a frequency resolution of 32-bits, and the baseband outputs pass through a programmable gain stage before being rounded to their final 16-bit result. Each channel has an independently programmable 16-bit gain control.

The model 4954-430 accepts 16-bit input real or complex data and generates 256 independently tunable 16-bit complex output channels. The core offers extremely fine tuning capability with 32-bit tuning resolution per channel. The IP is priced at $14,995. More information is available at www.pentek.com.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.