Tutorial: Improving the transient immunity of your microcontroller-based embedded design - Part 1 - Embedded.com

Tutorial: Improving the transient immunity of your microcontroller-based embedded design – Part 1

When it comes to protecting their designs from a variety of transientelectrical disturbances, developers of microcontroller-based embeddedsystems in consumer, industrial, and automotive electronics are caughtbetween the rock and the hard place.

On the one hand, more sophisticated and noise-sensitivemicrocontrollers (MCUs), with highintegration, tighter process requirements and lower voltagerequirements are moving into designs that are increasingly hazardouswith respect to electromagneticinterference (EMI) and electrostaticdischarge (ESD ) .

On the other, increased competition, as well as market regulatorypressures, are forcing original equipment manufacturers (OEMs) toreduce the cost of their products. As a result of this focus on costcontrol, implementing the necessary transientimmunityprotections toprevent application malfunction due totransients on power and signal lines is becoming ever more challenging.

The impact of increasing MCU sensitivity and low-cost applicationdesign is being felt in all markets: consumer, industrial, automotive,etc. While there are significant differences in the design and use ofproducts for these markets, the susceptibilities induced in allmicrocontroller-based applications are essentially the same. Typicalsusceptibilities include unexpected state changes on input pins (reset,interrupt request, or general purpose inputs), corruption of on-chipclock signals, or even damage to the silicon.

The pervasive impact of EMIand  ESD transients
In consumer electronics applications ,transient immunity is a challenge for both battery powered and AC mainspowered products. Battery powered products such as keyboards, mice,remote keyless entry systems, and remote controls are challenged byensuring the immunity of the application to ESD transients.

For example, an ESD directly to the product or to a nearby couplingplane has been seen to assert the reset function of an MCU bytemporarily changing the state of the RESET pin. In these cases, thereis typically a long trace between the RESET pin and an in-circuitprogramming header that serves as an antenna to receive the ESD energyand couple it to the RESET pin.

Likewise, an electrical fasttransient (EFT) injected on the AC power plug of an AC mainspowered product can couple to a reset trace by either radiation orconduction resulting in susceptibility. Self-compatibility is also ofgreat concern where the product contains inductive loads (motors,compressors, etc) that are switched.

Since electronics for industrialapplications is typically powered only from the AC mains, theyhave similar issues to those of consumer electronics products poweredfrom the AC mains. However, these issues are typically more severe thanin residential applications due to the presence of heavy machinery(large inductive loads) switching on and off the power distributionsystem for the factory.

The transient immunity issues in automotiveelectronics applications are also similar to consumerelectronics applications except for being powered by DC mains. This isbecause automobiles contain numerous switching inductive loads(alternator, compressor, solenoids, etc) that put transients on the DCmains. In addition, automotive applications are becoming increasingconcerned with ESD.

For example, a new application for MCUs is in remote tire pressuremonitoring systems (TPMS). This is a novel innovation but introducesnew ESD immunity issues. ESD near a TPMS device has been seen to causeboth upset and damage. Since it is almost impossible to ensure that anautomotive technician uses and ESD wrist strap, TPMS and otherautomotive electronics can easily be exposed to ESD in the ±25kV range during maintenance operations. For reference, commercialelectronics are typically required to be immune to ESD in the ±8kV range.

To meet the transient immunity challenge as traditional power supplydesigns and EMI controls are sacrificed for lower cost solutions, theembedded systems designers must employ new techniques and processes tomeet the applicable regulatory and market requirements for electromagneticcompatibility (EMC) .

Achieving transient immunity in a low-cost embedded application canbe a difficult and time-consuming process, particularly if notaddressed early and often in the design of an application. In addition,making the mistake of not addressing transient protection as close tothe AC or DC mains as possible will also adversely affect thecomplexity of EMC protection. The initial design of an embeddedapplication should maximize EMC so that design budgets and productionschedules are met without delays at the EMC compliance stage.

However, there are practical hardware design techniques that can beemployed to provide cost-effective protection for EFT,ESD and other power line or signal line transients of short duration.In addition, the EFT or ESD performance of a system can be dramaticallyaffected by the choices made in the software architecture andapplication functionality.

Software techniques should be viewed as a necessary but last line ofdefense against adverse system reaction to EFT or ESD events. Thesoftware can affect how the system will react to a disturbance if itreaches the MCU but the hardware PCBboardand system hardwaredesign should diminish or eliminatethe disturbance before it reaches the MCU.

Prioritizing the control of transient voltages and currents withhardware techniques is also important from the aspect of minimizingexposure of electrical and electronic components to over-specificationconditions that could result in accelerated failure rates or long-termdegradation.

Defining the problem
Low cost, microcontroller-based embedded applications are particularlysusceptible to performance degradation during ESD and EFT events. Thissensitivity to fast rise time transients is to be expected, even formicrocontrollers running at relatively low clock frequencies.

This sensitivity is due to the process technologies employed.Today's semiconductor process technologies for low-cost, 8-bit and16-bit MCUs implement transistor gate lengths in the 0.65?m to 0.25??mrange. These gate lengths are capable of generating and responding tosignals with rise times in the sub-nanosecond range (or an equivalentbandwidth of greater than 300MHz). As a result, an MCU is quite capableof responding to ESD or EFT signals injected onto its pins.

In addition to the process technology, MCU performance in thepresence of an ESD or EFT event is affected by the design of the IC andits package, the design of the printed circuit board (PCB), thesoftware running on the MCU, the design of the system, and thecharacteristics of the ESD or EFT waveform when it reaches the MCU. Therelative impact of each performance driver (where to focus effort formaximum effect) is shown in the pie chart in Figure 1, below.

Figure 1. Performance driver impact on transient immunity

Several facets of IC design other than physical gate length canaffect MCU performance during transients. These include the compositionof ESD suppression devices on input/output (I/O) pins and the layout ofI/O pin structures. ESD devices range from simple diodes to complexactive filters. Power supply rejection is accomplished through internalcapacitance and careful routing on the die. Physical separation of pininputs from active circuitry is a proven method to reduce transienteffects but at a greater cost penalty due to die size impact.

The choice of MCU package can also affect immunity performance. Thepackage type can have a great influence on PCB layout and composition.Surface-mount MCUs generally have smaller footprints than through-holepackages. This can reduce overall PCB dimensions and increase routingdensity, but it can also provide more space to implement board-levelsuppression techniques.

Areas of MCU Vulnerability
Considering that most MCUs are specified and designed to generate andrespond to signals with rise times comparable to ESD and EFT events,vulnerability to these events should be expected. Areas of MCUstypically vulnerable to ESD and EFT stresses include:

1) Power and ground pins
2) Edge sensitive digital inputs
3) High frequency digitalinputs
4) Analog inputs
5) Clock (oscillator) pins
6) Substrate injection
7) General purpose I/O (GPIO) with multiplexed pin functions
8) ESD protection circuitry

Some MCUs have multiple power and ground pins to isolate high speeddigital functions from low speed or noisy analog functions. Thesesupply pins should be filtered appropriately to prevent disturbances inone area from affecting another.

Low cost MCUs may only have a single set of power and ground pins,which makes isolation difficult, and makes filtering more important. Itis easy to understand that a transient that gets propagated to a supplyline can also disrupt internal circuitry that has no direct route tothe pin that was disturbed.

Edge sensitive inputs are particularly vulnerable to transients.These inputs are usually timer or external interrupt inputs. Even withexternal low pass filtering a sufficiently large pulse can injectenough energy into the input area to disrupt MCU operation. Pulses thatdon't disrupt the MCU can still be seen as glitches by the MCU. (Asoftware technique to filter out glitches is discussed later in thisseries ).

Figure 2. Transient generation of logic glitches

High speed digital inputs, such as clock and data inputs, are lesslikely to have low pass filteringand consequently can register transients as valid data pulses (see Figure 2, above) . Externalisolation techniques are necessary to eliminate this vulnerability.

Analog inputs are generally lower impedance than digital inputs andcan suffer physical damage if not protected during ESD and EFTtransients. However, on most MCUs the analog inputs are multiplexedwith general purpose I/O pins and have a small sampling window in whichthe lower input impedance is active. A transient appearing in an analoginput pin during an analog to digital conversion will result indistorted data due to the signal disruption. Effective softwarefiltering techniques exist to mitigate this vulnerability.

Most MCUs have a built-in oscillator amplifier so that an externalcrystal or resonator is all that is needed to ensure a stable highfrequency system clock. The oscillator pins can pass noise pulses asvalid clock edges and are considered to be the most vulnerable inputsto the system. Appropriate PCB layout is the preferred method toeliminate this risk.

Figure 3. Transient current injection paths inside the MCU

As shown in Figure 3 above ,transients can travel from the point of entry and affect circuits viaseveral paths. System input signals that exceed the power rails of theMCU will inject current into the I/O pin structure as soon as thesignal level exceeds the ESD protection diode's forward voltage.

The I/O pin structure and on chip ESD protection network candissipate small amounts of injected energy. However, if the injectedcurrent is greater than the local circuit can handle, this excessivecurrent can find alternate paths through the supply rails or substrateto disrupt other circuitry. Current injection is generally minimized byusing series resistors.

General purpose MCUs have I/O ports that can have more that onefunction multiplexed on a single pin. An electrical disturbance thatcauses enough energy to disrupt digital logic can also affect thecontrol circuitry that selects the pin function. The resulting faultcould change the pin state, the pin directionality, or the pinfunction.

Vulnerability is particularly troublesome for general purpose MCUsthat are designed to meet the needs of many applications. For theseMCUs, it is impractical or impossible to harden all vulnerable areaswithout adversely affecting functional performance in at least someapplications.

Application-specific MCUs can be hardened with greater success, butsome vulnerability will continue to exist if the operational frequencyor bandwidth of the MCU overlaps the bandwidth of the ESD and EFTsignals.

MCU Immunity PerformanceClassification
The immunity performance for integrated circuits is typicallyclassified into one of four categories as specified in IEC 62132-1 and shown in Table 1 below .

The classification applied is determined by the performance of theintegrated circuit in the presence of the disturbance signal (i.e theESD or EFT waveform). This performance is dependent on the type ofintegrated circuit and its functional and parametric operation asdocumented in its data sheet.

Table 1. Classification of IC EMC Degradation

Class Aperformance is the most desirable and is often required forsafety-critical applications. Of course, this level of performance isdifficult to ensure without taking proper steps in the design of theapplication. This is because any transient appearing at a pin that canbe processed by the input circuitry has the potential for beinginterpreted as data and corrupting program execution.

Class Bperformance is considered acceptable for most applications wherethe main requirement is for no user intervention to recover normalperformance. ClassC performance can be acceptable for particularapplications where operator intervention is not an issue, or where anexternal watchdog or supervisory circuit is used. Class D performance is not acceptable.

MCU Failure Modes
For MCUs, performance degradation can take many forms. Common forms oftemporary degradation include but are not limited to reset, latch-up,memory corruption, and code runaway.

MCUs with internal reset circuits can generally resume operationwithout operator involvement if the fault is an unexpected reset orcode runaway that is caught by a watchdog timer.

Recovery from latch-up and volatile memory (RAM, DRAM, etc.)corruption requires cycling the power to the system. Non-volatilememory (FLASH, EEPROM, ROM, etc.) corruption requires a more extensiveprocess of re-programming the system, which can be viewed as atemporary MCU degradation if the system can be re-worked, or as apermanent degradation if it cannot be re-worked.

Permanent degradation can include increased leakage current on I/Opins which can affect analog measurements, input impedances, and outputdrive strength. With increased leakage current, the electronic systemmay still operate within specification for a while, but it mayultimately fail due to damage from the transient stress. Another typeof permanent degradation found in transient environments is blown pinsdue to an electrical overstress.

Impact of MCU Design Trends
The MCU design trend that particularly impacts transient immunityperformance is the drive to continually reduce the minimum gate lengthof individual field effecttransistors (FETs), making them smaller and faster. This trendis the result of market pressure on semiconductor manufacturers toreduce the cost of their products by making die sizes smaller.

The result is that maintaining the immunity performance of MCUs inthe face of process technology advances is becoming increasinglydifficult. When coupled with continuing cost reductions by OEMs at theapplication or system level, the immunity problem becomes severe.

MCU designers are challenged to develop better methods to dissipatethe energy injected during a transient event. While they wouldappreciate more area in which to include transient suppressioncircuits, this is generally not allowed in order to keep the die sizeand cost to a minimum. Some of the remaining options available to thedesigner include modifying semiconductor attributes (doping andmaterials) and changing the vertical structure of the I/O pin.

Next in Part 2: Hardware Techniques- The basic circuit building blocks

Ross Carlton has specialized inall aspects of electromagnetic compatibility (EMC) since his graduationfrom Texas A&M University with a Bachelor of Science in ElectricalEngineering in 1985. He has been with Freescale Semiconductor for thelast eight years where he has led the EMC design, test and support ofFreescale's 8, 16, and 32-bit microcontroller products. In addition,Ross represents the U.S. as a Technical Expert to IECSubcommittee 47Aon integrated circuits where he is the project leader for IEC 61967-2,IEC 61967-3 and IEC 62132-2. Heis currentlyinvolved in developing transient immunity test methodologies forstandardization.

Theauthor would like to thank GregRacino and John Suchyta, 8-Bit Applications Engineer at FreescaleSemiconductor   for theirinputs and guidance. Their contributions were critical toensuring consistent and correct guidance.

1. Ross Carlton, Greg Racino,John Suchyta, Improving the Transient Immunity Performance ofMicrocontroller-based applications. FreescaleApplication Note (AN) 2764).

2. IEC 61000-4-2,Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurementtechniques – Electrostatic discharge immunity test, InternationalElectrotechnical Commission, 2001. 

3. IEC 61000-4-4,Electromagnetic Compatibility (EMC) – Part 4-4: Testing and measurementtechniques – Electrical fast transient/burst immunity test,International Electrotechnical Commission, 2001.

4. Ronald B. Standler,Protection of Electronic Circuits from Overvoltages, John Wiley &Sons, 1989, pp. 265-283.

5. Ken Kundert, “PowerSupply Noise Reduction”, The Designer's Guide , 2004.

6. Larry D. Smith,”Decoupling Capacitor Calculations for CMOS Circuits”, ElectricalPerformance of Electrical Packages Conference, Monterey CA,November 1994, Pages 101-105.

7. Ronald B. Standler,Protection of Electronic Circuits from Overvoltages, John Wiley &Sons, 1989.

8. Clayton Paul, Introductionto Electromagnetic Compatibility, Wiley & Sons, 1992.

9. Bernard Keiser,Principles of Electromagnetic Compatibility, Artech House, 1987.

10. T.C. Lun, “Designing forBoard Level Electromagnetic Compatibility”, MotorolaApplication Note (AN) 2321.

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