The first and best opportunity to eliminate conducted transientimmunity problems is at the point of power or signal entry into theapplication. If the immunity signal can be sufficiently suppressed atthis point, the remaining hardware and software techniques are notnecessary.
The impact of this is threefold: the risk on noncompliance isreduced or eliminated, less cost and effort will have to be expended inother areas of the design, and schedule delays due to transientimmunity issues can be eliminated with a high probability.
Examples of point of entry power filters and signal line filters areshown in Figures 1a, 1b, and Figure2, below , respectively. Power filters are readilyavailable from numerous vendors in both standard and custom packages.Filter performance can also be selected from standard offerings orcustomized for the particular application.
|Fig. 1a. Standard point of entry power filters||Fig. 1b. Custom point of entry power filters|
While many prepackaged filter solutions exist, they are by no meansnecessary. Filters implemented with discrete components can easilyachieve the necessary performance with more flexibility and potentiallylower cost.
|Fig. 2. Point of entry signal line filter examples|
Even filters built manually on printedwiring boards (PWBs) areeffective if located properly in the application. Any filter needs tobe placed as close as possible to the power or signal point of entryinto the application.
The primary consideration is to filter the undesired noise from thepower or signal lines before it can either couple to other wires withinthe application or conduct onto the application PCB as shown in Figure 3, below.
|Figure 3. Point of entry filter placement|
If power and signal connections to the application are not optimizedfor transient suppression at the point of entry, the compliance problemincreases in complexity because control of the immunity signals hasbeen lost. The result is that all of the remaining hardware andsoftware techniques may be needed to ensure good electromagneticcompatibility (EMC)performance.
System Connector Location
If power and signals are filtered at their point of entry into theapplication, the location of connectors is not critical. However, ifthe power and signals are not filtered, connector location becomes veryimportant. In this case, connectors should be located so that thecable's length between the application chassis and the connected loadis as short as possible.
A short connection will reduce the amount of energy radiated intothe chassis but will have no effect on the conducted immunity signal.In addition, physically separate or isolate power connectors fromsignal connectors as much as possible.
System Cable Routing
Where cable lines are unfiltered, never, under any circumstances, routepower lines and signal lines in the same cable bundle. Doing so willonly ensure that the noise on the power/signal lines will be coupled tothe other signal/power lines in the bundle. Failing to follow this rulewill serve to maximize the complexity of the immunity problem byensuring many more noisy signals to suppress in the system.
Where cable lines are filtered, power and signal lines may be routedtogether in the same cable bundle only if there is no possibility ofcreating a self-compatibility problem. For instance, aself-compatibility problem may exist if the application containssubsystems or components that generate transient noise as a result ofnormal operation (i.e. ” relays, motors, compressors, etc.). If thepossibility of a self-compatibility problem exists, default to the rulefor unfiltered lines.
System Component Placement
The placement of subsystems, components or cables is important “particularly for self-compatibility. Noisy subsystems, components orcables should be physically isolated from sensitive electronics, suchas the microcontroller (MCU), to minimize radiated noise coupling.Physical isolation can take the form of separation (distance) orshielding.
Bypassing is the reduction of high frequency current flow in a highimpedance path by shunting that path with a bypass, typically acapacitor4. Bypassing is used to reduce current noise on power supplylines by reducing the time rate of change of current (di/dt ) being drawn through theinductance of the power distribution system. A capacitor performs thisfunction by providing a local source of high frequency current at theintegrated circuit (IC).
Inadequate bypassing increases system noise margins and ultimatelyleads to incorrect, unreliable, or unstable operation. For a bypassnetwork (a capacitor or group of capacitors) to perform properly, thefollowing conditions are necessary:
1) The capacitance must besufficient to provide the needed transient current to the load,
2) The impedance between thenetwork and its load must be very low, and
3) The loop area of the network mustbe as small as possible.
The size of the required capacitance can either be calculated usingreadily available formulas and the characteristics of the decoupled MCUor, even better, by experimentation and measurement. The following setof equations will give the designer a good starting point for selectingthe correct decoupling capacitance. The equations and associated stepsare as follows:
1. Determine the average powersupply current (Iavg ),
This parameter can be measured or calculated from the MCU electricalspecification by
where P avg is the average power dissipatedby the MCU, and V DD is the power supply voltage. Theaverage power is typically referred to in Freescale electricalspecifications as the dissipated power (P D ), which consists of both internalcore power (P INT ) and input/output (I/O) pin power(P I/O ) such that
P D can be calculated from theequations provided in an MCU electrical specification or measured. P I/O can also be calculated or measured but, in some applications, it can beneglected
2. Calculate the charge (¾Q ) to be drawn from thedecouplingcapacitor at the clock edge by
where f c is the clock frequency.
3. Calculate the capacitance (C) needed to source the needed chargewhile maintaining the voltage supply to within some ripplespecification by
where n is the supplyvoltage ripple in percent (%).
4. Select a package with aresonant frequency (f o )that is at least twice the clock frequency by
where L package is the series inductance onthe selected package. This inductance is typically associated with thepackage leads and aspect ratio ” shorter and wider leads will provideless inductance and a higher resonant frequency. The impedance of acapacitor over frequency (Z C(jw) ) is calculated by
= 2 x x f
Decoupling is the isolation of two circuits on a common power supply toprevent the transmission of noise. The decoupling circuit is typicallya low-pass filter. The low-pass filter is usually not symmetrical ” theisolation is not equal in both directions though the network.Decoupling achieves circuit isolation by utilizing shunt elements(capacitors, TVS, etc.) and/or block elements (resistors, inductors,ferrites, etc.) to limit the high-frequency content of transmittedsignals or power. Noise that is not shunted to its return path will beattenuated by the series impedance.
Bypassing and Decoupling Layout
To achieve optimal performance of the power distribution network, anyshunt element connected between any of the MCU pins and V SS should be connected to the MCU V SS pin(s) using planes or short, widetraces.
The impedance of these connections and, therefore, the performanceof the shunt element, can be adversely affected by the layout patternsused on the PCB to mount the component and connect it to the MCU. Theselayout patterns add series inductance to the impedance of the networkresulting in a lower resonant frequency. A comparison of componentlayout patterns is shown in Figure 4,below.
|Figure 4. Layout pattern inductance comparison|
Reducing the impedance of the power distribution network can also beachieved by minimizing the loop area of the filter network. An exampleof filter network (decoupling capacitor) current loop area is shown in Figure 5, below.
As the length ofthe trace (x) between the MCUand decoupling capacitor increases, theloop and series inductance also increase. This reduces the efficiencyof radiated emissions and susceptibility coupling.
|Figure 5. Decoupling loop area|
MCU Oscillator Circuit
Two types of clock sources are typically used for microcontroller-basedapplications: mechanical resonant devices such as crystals and ceramicresonators; and passive RC (resistor-capacitor) oscillators. Thecharacteristics of these clock sources and other commonly used clocksources are described in Table 1,below .
The optimum clock source for a particular application will depend oncost, required accuracy, desired power consumption, and therequirements of the operational environment ” which includes EMC.
|Table 1. Characteristics of Clock Sources (Source: Maxim application note AN2154 “Microcontroller Clock -Crystal, Resonator, RC Oscillator, or Silicon Oscillator?”, 02 July 2003, http://www.maxim-ic.com. )|
Normal values of feedback resistor in an external oscillator circuitdo not affect noise susceptibility. However, noise susceptibility(ability of spurious noise to disrupt the crystal) is affected when theseries resistance is too high.
The choice of bias resistor and load capacitors in the oscillatorcircuit (in the case of the Pierce oscillator configuration) can lowerthe signal amplitude at the oscillator input pin (typically OSC1 or EXTAL ) whichincreases the chance that input noise can disrupt the signal. Insystems with electromagnetic susceptibility concerns, an oscillatorconfiguration should be chosen which results in a large amplitudesignal at the oscillator input pin.
In addition, lower frequency crystal oscillator circuits result insignals with slower rise and fall times and the oscillator input pin.This increases the potential of noise affecting the input signal.
The oscillator circuit is often a primary source of susceptibilityin an application. To maximize immunity, the oscillator componentsshould be closely grouped and located next to the oscillator pins ofthe MCU. All traces associated with the oscillator circuit should be asshort as possible.
The oscillator circuit should be surrounded by guard tracesconnected to the V SS pin of the MCU with short groundtraces or a ground plane. The oscillator circuitry should also bephysically isolated or shielded from any I/O signal traces routed tooff-board connectors.
Whether at the system or PCB level, transients on input signals createa particularly challenging problem. Inputs are typically coupled tosupply and ground through electromagneticinterference (EMI) andelectrostaticdischarge (ESD) control devices in addition to beingconnected to circuitry that will operate on the state of the signal.
As a result, inputs require the same considerations as power pinsbut include additional considerations tied to the functionalrequirements of the application.
EMI and ESD control devices must provide the required level ofprotection without degrading the input signal or the characteristics ofthe receiving circuitry beyond specification. For circuitry with anoperating bandwidth outside the noise bandwidth of the transientwaveform, protection can be achieved by the use of low-pass, high-pass,or band-pass filters.
For circuitry with an operating bandwidth within the noise bandwidthof the transient waveform, implementing effective protection without,at least temporarily, degrading performance can be very difficult oreven impossible. In this case, the designer may have to rely onsoftware techniques discussed later.
The standard protection for inputs is the low-pass filter as shownin Figure 6, below. The seriesresistance limits the injected current. The parallel capacitor shuntsthe transient current into the ground system as it attempts to hold thevoltage to its steady-state value. The values of resistance andcapacitance can be varied to either maximize protection or minimizeimpact on the input signal. While typically referenced to V SS (as shown), the capacitor can also be referenced to V DD .
|Figure 6. Typical low-pass filter transient protection on input pin|
Additional strategies for limiting transients on inputs include:
1) Clamp the input voltageusingtransient voltage suppressor (TVS) devices.
2) Limit the input currentusing series resistance or impedance.
3) Shield input cables withbraided or solid shields.
4) Shield PCB traces with guardtraces, microstrip or stripline techniques.
5) Utilize line terminations toreduce ringing and overshoot.
6) Terminate unused input pinsto V DD or V SS .
If sensitive input signals are to be routed off the PCB, place theMCU near the off-board connector. If not, place the MCU where the tracelengths of these signals will be as short as possible.
Next in Part 4: PCB Power Supply andFloor Plan Opportunities
To read Part 1, go to: Definingthe Problem
To read Part 2, go to: HardwareTechniques – The basic circuit building blocks
Ross Carlton has specialized inall aspects of electromagnetic compatibility (EMC) since his graduationfrom Texas A&M University with a Bachelor of Science in ElectricalEngineering in 1985. He has been with Freescale Semiconductor for thelast eight years where he has led the EMC design, test and support ofFreescale's 8, 16, and 32-bit microcontroller products. In addition,Ross represents the U.S. as a Technical Expert to IECSubcommittee 47A on integrated circuits where he is the project leaderfor IEC 61967-2, IEC 61967-3 and IEC 62132-2. He is currently involved indeveloping transient immunity test methodologies for standardization.
Theauthor would like to thank Greg Racino and John Suchyta, 8-Bit Applications Engineer atFreescale Semiconductor for their inputs and guidance. Their contributions were critical toensuring consistent and correct guidance.
1. Ross Carlton, Greg Racino,John Suchyta, Improving the Transient Immunity Performance ofMicrocontroller-based applications. FreescaleApplication Note (AN) 2764).
2. IEC61000-4-2, Electromagnetic compatibility (EMC) – Part 4-2: Testing andmeasurement techniques – Electrostatic discharge immunity test, InternationalElectrotechnical Commission, 2001.
3. IEC61000-4-4, Electromagnetic Compatibility (EMC) – Part 4-4: Testing andmeasurement techniques – Electrical fast transient/burst immunity test,International Electrotechnical Commission, 2001.
4. RonaldB. Standler, Protection of Electronic Circuits from Overvoltages, JohnWiley & Sons, 1989, pp. 265-283.
5. KenKundert, “Power Supply Noise Reduction”, The Designer's Guide , 2004.
6. LarryD. Smith, “Decoupling Capacitor Calculations for CMOS Circuits”, ElectricalPerformance of Electrical Packages Conference, Monterey CA,November 1994, Pages 101-105.
7. RonaldB. Standler, Protection of Electronic Circuits from Overvoltages, JohnWiley & Sons, 1989.
8. Clayton Paul, Introductionto Electromagnetic Compatibility, Wiley & Sons, 1992.
9. BernardKeiser, Principles of Electromagnetic Compatibility, Artech House,1987.
10. T.C.Lun, “Designing for Board Level Electromagnetic Compatibility”, MotorolaApplication Note (AN) 2321.