Ubiquify adds PHY analyzer to its lineup of DDR IP and tools

At the Design Automation Conference  in two weeks in San Francisco, Ca. Ubiquify will show off its just released UniquiPHY DDR System Analyzer (DSA) software package.

It provides designers with a suite of automated DDR analysis, visualization and debug tools for implementing its DDR IP building blocks capable of performance in silicon of 2800 megabits per second (Mbps).

According to Venkat Iyer, chief technical officer at Uniquify , DSA complements its adaptive PHY technologies, dynamic self-calibrating logic (DSCL) and dynamic adaptive bit calibration (DABC), by giving DDR designers a powerful, automated analysis and debug tool that interacts directly with the UniquiPHY DDR PHY.

“It allows the user to directly control PHY behavior and run numerous analyses, including trim and margin tests, DLL step-size tests, and general initialization and read/write tests,” he said.

The streamlined analyses it provides, said Iyer, give the DDR design team detailed insight into the DDR system performance and margins and also provides detailed information that speeds DDR system debug.

In addition to specific DDR analyses, DSA provides other useful system-level functions, such as verifying board connectivity and quality such as deskew. DSA can also be used to help evaluate the performance and quality of different DDR SDRAM components from either different vendors and/or different speed grades.

The UniquiPHY DDR System Analyzer is available as an accessory to the UniquiPHY family of DDR PHY IP.

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