Digital designers may be all too familiar with the challenges of routing high-speed digital lines between analog-to-digital converters (ADCs) and logic devices. Great care must be taken to ensure sufficient spacing between the high-speed traces as well as ensuring the digital signals do not cross analog boundaries. Poor layout will result in the digital switching noise feeding back into the ADC's analog inputs, degrading the overall system performance.
With board real estate at a premium and FPGA pins a valuable commodity, the advantages of serial data-converter interfaces over parallel are clear. Typical serial communication of high-speed digital data used in ADCs requires three pairs of transmission lines for low-voltage differential signaling (LVDS), with one pair for the data itself.
In order to accurately collect this data, a data clock is required. To establish data-sample boundaries, a framing clock is also required for frame alignment. For high-speed ADCs, aligning the data clock, the frame clock, and the data usually requires a Delay Lock Loop (DLL) in both the transmitter and receiver to align the data clock properly. This alignment becomes very difficult at gigahertz speeds. Ultimately, this 6-wire method of serial transmission is not generally done above 1.2 GHz, limiting either the speed of an ADC, or its resolution.
8B/10B encoding, originally invented in the 1980s by IBM, eliminates the need for a frame clock and a data clock, which makes single transmission-line-pair communications possible at frequencies above 2 GHz (Figure 1 ).
Figure 1: Traditional serial vs. 8B/10B encoding
(Click on image to enlarge)
The unique features of 8B/10B encoding allow the data clock to be embedded in the data itself, and the framing to be maintained with COMMA characters through initial frame synchronization.
Only recently has a specification been developed that defines the protocol and electrical characteristics required to standardize the implementation of this coded interface for data converters. JEDEC specification JESD204 has enabled a new generation of faster, more accurate serial ADCs, such as Linear Technology's LTC2274, 16-bit, 105 Msps ADC.
Advantages over typical 6-wire serial transmission
The 8B/10B encoded data is friendly to clock-recovery circuits because it is run-length limited. It also accommodates AC coupling because it is DC balanced. 8B/10B encoding involves transforming an 8-bit octet into a 10-bit code group. In each code group, the difference between the number of ones and zeros is never more than two. By monitoring the number of ones and zeros in consecutive code groups, a running disparity is calculated.
The transmitter and receiver use this disparity to encode and decode the data. For each input octet, there are two possible 10-bit output codes. The selection of the code to be transmitted is dependent on the running disparity, and is intended to keep the average number of ones and zeros equal. This property of 8B/10B encoding ensures the DC offset of the signal to be zero.
Once the data is encoded, it is serialized and transmitted, beginning with bit zero of the first code group. The JESD204 specification requires that the first code group corresponds to the most significant byte of data. The second code group corresponds to the least significant byte of data. Combined, these two code groups make up one frame of data, which constitutes one sample from a 16-bit ADC (Figure 2 ).
Figure 2: Evolution of one transmitted frame using 8B/10B encoding
(Click on image to enlarge)
The LTC2274, for example, samples at 105 Msps which, after encoding, produces a serial stream of data transmitted at 2.1 Gbps. At this speed, 8B/10B encoding and its unique properties make it possible to reliably transmit serial data over a 2-wire interface.
Though the clock may be recovered from the data stream with a PLL, it is still necessary for the receiver to determine the location of the frame boundaries. The JESD204 standard defines a synchronization process to establish initial frame alignment between the transmitter and the receiver. When the receiver is in need of synchronization, it will request this action by activating the synchronization input to the ADC. The ADC will then transmit a series of predetermined 8B/10B control symbols, also referred to as COMMA characters, so the receiver may identify the frame boundaries.
The JESD204 specification designates the K28.5 control symbol as the comma to be used for initial synchronization. When a synchronization request is received by the LTC2274, a series of K28.5 COMMA characters are transmitted until the receiver receives at least four valid K28.5 code groups, after which the receiver will de-assert the synchronization request signal. Upon deactivation of the synchronization request, the LTC2274 will continue to transmit the synchronization preamble until the end of the frame.
At the start of the next frame the LTC2274 will transmit data characters. This ensures that the data always begins in the same fashion, with the 1st code group associated with the most significant octet and the 2nd code group associated with the least significant octet (Figure 2). By using these COMMA characters to align the data, the need for a frame clock is eliminated. By using synchronization and run length limited 8B/10B encoding, serial transmission without using a bit clock, or a frame clock becomes possible.
Another advantage to using an 8B/10B encoding is that it is DC balanced. This is because the running disparity is used to maintain an equal number of ones and zeros over two alternate code groups, so the DC average of the signal is statistically zero. This allows single pair transmission lines to be used with transformers, optic couplers, DC blocking capacitors, and other high pass devices.
The JESD204 specification also outlines an optional scrambler that scrambles the data before it is encoded for transmission. This helps to avoid unwanted spectral peaks that can occur with high speed serial transmission. By scrambling the data, the octets that are encoded are data independent, which will eliminate spectral artifacts that can occur with certain data dependent signals.
The data is scrambled using a 1+x14 +x15 polynomial. This pseudo-random pattern repeats itself every 215 -1 cycles. The nature of this polynomial and scrambling scheme is that it can be used with a self-synchronous descrambler. The FPGA must have a descrambling algorithm to descramble the data after the 8B/10B decoder. This scrambling feature is designed into the LTC2274 as an option that can improve performance in certain situations.
Frame Alignment Monitoring
It may be desirable to check synchronization of data periodically. If the receiver requests a synchronization pattern from the transmitter in the normal fashion, there will be a loss of data associated with the transmitter sending a synchronization preamble. To prevent this loss of data, the JESD204 specification defines an alternative method of frame alignment, available in the LTC2274 through its Frame Alignment Monitoring (FAM) mode. This mode allows synchronization to be checked, without losing data, or without asserting the synchronization request input on the ADC. The JESD204 standard defines two methods of frame alignment monitoring (Figure 3 ).
Figure 3: Modes of frame alignment monitoring for data resynchronization
(Click on image to enlarge)
The first frame-alignment mode occurs when the data is not being scrambled. When the second code group in the current frame is equal to the second code group in the previous frame, the current code group will be replaced by K28.7. It is then the responsibility of the receiver to replace the K28.7 octet with the octet from the previous sample (Figure 3). If a third 2nd data octet is equal to the previous two, the actual octet will be transmitted. This mode of frame alignment is highly dependent on the data, and is not guaranteed to occur within any length of time.
The second frame alignment mode occurs when the data octets are scrambled prior to encoding. Whenever the 2nd code group of any frame is equal to D28.7, it will be replaced by K28.7. The receiver will then need to replace the K28.7 with the correct data character, D28.7. Since the effects of the scrambler are random, this method of frame alignment is less data dependent. Statistically, a K28.7 should occur 1 out of every 256 frames.
In either mode, it can be determined that there is an error if the control character K28.7 is found in the 1st octet. If this occurs, the receiver can either realign the frame or activate the synchronization request signal to resynchronize with the transmitter. When realigning the frame without initiating a synchronization request, the K28.7 should always appear in the second code group. If it is found in any other position, the following code group will signify the beginning of the first code group of the next frame. This feature allows for data resynchronization without loss of data from the ADC.
If the received data is shifted by one of more bits, this will result in invalid 8B/10B code groups. The receiver should then reassert the frame synchronization request signal which will cause the transmitter to send a stream of COMMA characters. If the data shifts by a whole code group, frame alignment monitoring can be used to detect this shift. A shift in the data of a whole code group will result in a corruption in the data that digital signal processing should be able to detect.
Using 8B/10B encoding for high-speed serial-data transfer, ADCs can now operate at higher sampling rates, and with greater resolutions. The LTC2274 from Linear Technology Corp. is a 105 Msps, 16-bit ADC that uses 8B/10B encoding to transmit its 16-bit output word serially to the receiver with a data output rate of 2.1 Gbps (20 encoded bits at 105 Msps).
The JEDEC serial interface is compatible with many FPGA high-speed interfaces including Xilinx's Rocket IO, Altera's Stratix II GX I/O and Lattice's ECP2M I/O. Reference designs using the LTC2274 are already available from each of these FPGA manufacturers.
One of the biggest challenges in the design of these new converters was achieving the high AC specifications while integrating the high-speed serial interface on the same die. The LTC2274 achieves signal to noise ratio (SNR) performance of 77.6 dBFS (full scale) and spurious free dynamic range (SFDR) of 100 dB at baseband (Figure 4 ).
Figure 4: LTC2274 128 KPoint FFT, with Fin=4.93 MHz, Fs=105 Msps
(Click on image to enlarge)
These AC specifications enable low-level signals to be resolved in the presence of large interferers or blockers, which is especially critical for multi-channel receiver applications. Ultralow jitter of 80 fsecRMS enables undersampling of input frequencies up to 500 MHz while maintaining good noise performance, allowing the ADC to sample closer to the antenna.
With the LTC2274, serial test patterns can be produced to facilitate testing of the serial interface and verify bit error rate (BER). This feature is invaluable for debugging the interface, but is not required by the JEDEC specification.
ADCs such as the LTC2274 with its serial interface make excellent sense for cost-sensitive applications, where FPGA pin count dominates the cost of the design. High-performance communications equipment such as basestation receivers and digital predistortion transmitters can achieve significant cost savings using the dedicated SerDes port on the FPGA, while benefiting from the high SNR and SFDR performance for multi-carrier receiver designs. Spectrum analyzers can improve overall system performance with the capability to isolate the digital and analog circuitry. Multichannel applications such as ATE and medical imaging will benefit from the reduced pin count for ease of routing and additional space savings.
The JESD204 standard for data converters makes it possible for high-speed, high-resolution ADCs to transmit high-speed data across a single pair of transmission lines. By using a run-length-limited signal to recover the data clock, and COMMA characters for initial frame synchronization, the difficulties of standard serial transmission are mitigated. As a result, the 8B/10B signal has a DC offset of zero, and can be transmitted through any high-pass device, such as DC blocking capacitors. The JESD204 standard also allows for frame alignment without loss of data through frame alignment monitoring. It also provides a means of reducing non-harmonic spurs by using a scrambling polynomial.
About the author
Clarence Mayott is an applications engineer for Linear Technology Corp., Milpitas, CA. He received his BSEE from the California Polytechnic University in San Luis Obispo.