Understanding ADC code error rate - Embedded.com

Understanding ADC code error rate

As high-speed analog-to-digital converters (ADCs) have increased in sampling rate, so has the problem of code errors — also known as sparkle codes — in the ADC’s output data. A code error is defined as an error in the output code of an ADC that exceeds a defined threshold. The threshold is most commonly defined as the level where an error exceeds the expected amplitude of the ADC’s noise such that the error can be easily identified in the presence of noise.

Another way to explain this definition of the error threshold is that the error amplitude occurs with a probability exceeding the expected probability of that amplitude given the ADC’s assumed Gaussian distributed noise. Fig. 1 shows an example code error found in the output samples of an ADC. The erroneous sample is clearly visible when compared to the ideal sine wave fit and far exceeds the noise of the other samples in the plot.


Fig. 1: Example of an ADC output with a code error.

An ADC’s code error rate (CER), also sometimes called word error rate (WER) or metastability error rate, is defined as the average number of errors per sample and is measured by counting the average number of samples between consecutive errors. It is most often defined as an order of magnitude, such as 10 –12 errors/sample. The average time between errors, therefore, depends on the sampling rate of the converter. The measured CER is accurate only when the ADC is running at the sampling rate at which the CER was measured. In general, reducing the sampling rate can improve the CER by orders of magnitude.

Let’s take a look at where code errors come from to see why sampling rate is a major factor.

What makes an ADC sparkle?
A multistep ADC architecture, such as a pipelined flash ADC or a successive approximation register (SAR) ADC, converts the sampled voltage to digital bits in stages, and each consecutive stage relies on the result of the previous stage. Consider a basic pipelined flash high-speed ADC, as shown in Fig. 2 . This simplified ADC shows two conversion stages wherein each successive stage produces a digital code that more finely estimates the input signal.

The operation of the shown ADC is as follows:

  • The first stage samples the input voltage and coarsely converts the analog input signal to a digital code using the first-stage ADC. The flash ADC in this stage works by comparing the sampled voltage against static voltage references, generated from the ADC’s main reference voltage (V REF ), using high-speed comparators. The output of the flash comparators is a thermometer-encoded digital sample representing the input voltage.

  • The converted thermometer code is then sent directly to the first-stage DAC. This DAC outputs the analog voltage, which corresponds to the coarsely converted sample.

  • Subtracting the output of the first-stage DAC from the original input voltage results in the quantization error voltage or residue voltage (V RES ). The residue is then amplified and resampled (pipelined) for the second stage.

  • The second-stage ADC quantizes V RES to obtain a more accurate (higher-resolution) estimate of the original analog input voltage.


Fig. 2: Example of a pipelined flash ADC architecture block diagram.

The V RES creation process introduces a high-speed decision loop. Within one sampling clock period, the sampled voltage must be converted to a digital code by the first-stage ADC. The digital code must be output from the first-stage DAC, subtracted from the original input voltage and resampled by the second stage. The high-speed decision loop introduces code errors because the comparator in the flash ADC has a settling time that is a function of the difference between the sampled voltage and V REF .

More simply, a comparator takes longer to settle when the input voltage (V CAP1 ) is close to the reference voltage (such as 7 * V REF /8) of the comparator. Theoretically, if V CAP1 is infinitesimally close to the comparator’s reference voltage, the comparator will never settle because it will be operating in its linear region.

Noise will prevent this from actually occurring, but if the comparator does take too long to settle, then the first-stage DAC may use the incorrect digital code to output the quantized analog voltage. The result is a V RES that doesn’t match the first-stage ADC’s actual digital output code. The second-stage ADC then converts the wrong V RES , which results in a code error.

What affects CER?
You should now have enough detail to be able to draw some conclusions on what affects the CER. The CER clearly depends on the sampling rate. A faster sampling rate reduces the time in which the decision loop has to make a decision. Less time to make a decision results in exponential increases in the probability that the comparator has not settled in time.

–Matt Guibord is a systems engineer in high-speed converters at Texas Instruments.

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