EMIF64 is a proprietary interface developed by Texas Instruments, whichhas served the industry well for many years. However it is now beingused in applications for which it was never intended, such as DSP toDSP links.
The EMIF standardrepresentsa mature and stable parallel external memory interface, which hasproved useful for many applications. However its capability is limitedto master-only, which requires expensive CPU interrupt service routinesin order to transfer data into the device from other masters in thesystem.
A large software overhead can also be required to support the EMIFinterface, depending on the size and frequency of the data transfers.This is demonstrated in Figure 1 below ,which shows a traditional EMIF application example, in the form oftransferring results from a CR ASIC to DSP by the CPU Interrupt + EDMAMethod.
|Figure1: Block diagram showing the transfer of results from a CR ASIC to DSPby the CPU Interrupt + EDMA method|
Rethinking your design options
However, by choosing a state-of-the-art series interface such as SerialRapidIO, a number of general advantages are gained:
*Configurability and performance ” RapidIO supports 1.25, 2.5 and3.125Gbaud rates per link, and up to eight 4x links or sixteen 1xlinks. It is deterministic and low latency, and provides a non-blockingswitching fabric.
* Control “RapidIO features configurable CPU Interrupt control and support forerror management, as well as support for congestion control viaperformance monitoring statistics. It also provides CRC handling forhardware error recovery.
* Softwaresupport ” The inclusion of hardware-terminated endpoints resultsin a low software overhead. RapidIO also requires only low-levelconfiguration and functional support, while offering a highlyabstracted message-passing API. It also has the advantage that the CPUoverhead is not dependent on the size of the data transferred, forexample with small control messages.
Figure 2 below shows thesame application as Figure 1 when implemented using Serial RapidIO. Thespecific benefits of taking this approach in preference to EMIF64 canbe summarized under the following headings:
* Flexibility “The limitations of EMIF64 include the fact that it is not an openstandard interface, and has its bandwidth limited to 8Gb/s half duplex.It is also not a scaleable solution. Serial RapidIO on the other handhas an open standard interface, scaleable bandwidth up to 20Gb/s andscaleable architecture.
* Performance ” EMIF64 is a lossy system, which does not store and forward nor doesit offer data prioritization. There is also non-deterministic latencyacross switch. Serial RapidIO is a lossless system with guaranteedpacket delivery that has four priority levels available. Deterministiclatency across the switch is featured.
* Developmentcosts ” When an EMIF64 interface is used, FPGA design andverification resources required. The amount of test bench effortentailed should not to be underestimated either, and finally continualproduct support is required.
With Serial RapidIO however, no silicon design effort is required,and the solution is less costly to implement due to the higher relativeI/O requirements of EMIF64. At the same time PCB complexity is reduced- a single 64 bit EMIF interface requires approx 97 pins, meaning thatan eight port switch requires 776 interface pins alone – giving aconsequent reduction in cost.
* Otherbenefits ” Serial RapidIO provides CRC handling for hardwarebased error recovery, whereas there is no error detection/correctionavailable with EMIF64. The latter also offers no status oracknowledgement feedback, while Serial RapidIO provides errormanagement and reporting functions. Furthermore the wide parallelinterfaces consume more PCB space than the serial alternative.
|Figure2: Block diagram showing the transfer of results from CR ASIC to DSP byDirect I/O using RapidIO|
One area where the two solutions are more or less equal is that ofpower requirements. The endpoint power is approximately the same whenconfigured with equivalent bandwidth settings.
EMIF has a half-duplex bandwidth of 8Gb/s when operating in 64-bitmode at 133MHz. Serial RapidIO has a full-duplex bandwidth of 4Gb/swhen in x4 mode at 1.25Gb/s. Switch power is also approximately thesame, although this does depend on how the FPGA is implemented, andwhich features are included.
Figure 3 below shows a blockdiagram of a 80Gb/s full-duplex Serial RapidIO switch thatis Open Standard compliant and also compliant to the Serial RapidIOInterconnect Specification V1.3, the most recent version.
|Figure3: The Tundra Tsi578 Serial RapidIO Switch|
A highly scalable solution for mesh, fabric and aggregated systems,this configuration provides designers and architects with configurationoptions to match the precise I/O bandwidth needs of a wide range ofnetworking, wireless and video infrastructure applications.
It is configurable with up to eight 4x links or up to sixteen 1xlinks, and each 4x link is decomposable into two 1x links. The switchsupports 1.25, 2.5 and 3.125Gbaud rates, with each port configurable to1.25, 2.5 or 3.125Gb/s. The ports are completely independent and theswitch supports mixed speed and width configurations.
Ease of use features include 'hot swap' – live insertion andextraction of field replaceable units. In terms of general performance,the switch features low latency due to packet cut-through, and offersfull duplex operation with line rate termination and a non-blockingswitch fabric, and prevents head-of-line blocking.
Featuring an integrated programmable XAUISerDes this third-generation switch uses innovativeswitching fabric management to increase the data throughput ofnext-generation communication infrastructure platforms, including ATCA and MicroATCA applications.
These platforms benefit in particular from the ability of the switchto route packets to over 64,000 endpoints, independent unicast andmulticast routing mechanisms, and error management extensions.
Multicast routing support enables simultaneous interconnection ofSerial RapidIO-enabled processors and peripheral devices at anaggregate bandwidth of 80Gb/s.
In addition the extensive non-blocking switching fabric managementfeatures include fabric monitoring to supervise and manage trafficflow, error management to provide the fabric controller with proactiveissue notification, a programmable buffer depth for guaranteedbandwidth and independent unicast and multicast routing mechanisms.
Traffic shaping is enabled by good visibility of throughput,enhanced performance monitoring statistics, and advanced schedulingalgorithms. The tremendous port flexibility of this design, combinedwith the use of very low power, high speed SerDes means that powerconsumption can be readily optimised.
To help simplify signal path routing, the switch also supports I/Olane swapping. Requiring 1.2V and 3.3V power rails and rated forindustrial and commercial temperature operation, this switch design canalso support the ACGA version of the IEEE 1149.6 JTAG standard forhigh speed interconnects.
The migration from a traditional DSP EMIF to a Serial RapidIO switchedapproach enables a robust, feature rich design that is scalable tomultiple DSP densities.
In addition, a Serial RapidIO switch is less than half the cost of aFPGA EMIF64 switch, and requires significantly fewer developmentresources. DSP software support is greatly reduced when using ahardware terminated Serial RapidIO endpoint. Finally, a cumulativesaving in MIPS through a DSP cluster can enhance overall systemperformance and value.
Wayne Cullen isField Application Engineer EMEA at Tundra Semiconductor.