USB 3.0: Delivering superspeed with 25% lower power - Embedded.com

USB 3.0: Delivering superspeed with 25% lower power

USB 3.0 offers new opportunities to boost battery life for both host and endpoint functions thanks to comprehensive power management features that operate autonomously at the hardware level.

The desire to extend battery life in the fast growing mobile computing market has placed a new spotlight on power management within portable systems. Developers of laptops, netbooks, smart phones, and tablets now scrutinize every amp of power usage at the system level in their drive for better power efficiency. The introduction of USB 3.0 brings new opportunities to boost battery life for both host and endpoint functions thanks to comprehensive power-management features that operate autonomously at the hardware level.

Designed to overcome the drawbacks of the Advanced Power Management (APM) model, the Advanced Configuration and Power Interface, or ACPI, was introduced in 1997. The specification brings some level of power awareness to the BIOS, system hardware and software. ACPI relies on tables in the BIOS to define the power modes for individual peripherals. The operating system then uses these definitions to decide when to switch a device, or the entire system, from one power state to another.  USB 2.0 has supported this software-based approach relying on suspend-resume commands to place the universal serial bus in a power-reduced state. However, these ACPI-based implementations have been plagued by stability and latency issues.

Implementing an effective power-management policy for interfaces such as USB presents additional challenges. USB is one of the few peripheral buses that allow different types of devices with varying usage frequencies to attach simultaneously. Many of these USB devices experience extended periods of idle. In addition, developers must contend with the growing popularity of devices that draw power or recharge batteries over USB.

The USB 2.0 power-management model was enhanced with the introduction of Link Power Management (LPM) in the EHCI specification 1.1. The new LPM transaction is similar to the existing USB 2.0 suspend/resume capability, however—it defines a mechanism for faster transition of a root port from an enabled state (L0) to a new sleep state (L1). Implementing LPM requires changes at both the chip and software layers, which have slowed market adoption. Table 1 outlines the LPM entry and exit timing windows.


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USB 3.0: Designed for power efficiency
Recognizing that continued adoption of USB will require improved power efficiency, the USB Implementers Forum (USB-IF) has made power management a cornerstone to its next generation interface, SuperSpeed USB. For backwards compatibility, USB 3.0 devices are required to support both 2.0 and 3.0 link speeds. USB 3.0 devices will maintain separate controllers and physical layers for high/full speed and superspeed links. To ensure power savings gained while operating in USB 3.0 mode are not lost when 3.0 hosts are connected to legacy 2.0 devices, all USB 3.0 ports (host and device) are now required to support the LPM feature above when operating at high/full speed. Correct power-management operation in both legacy USB 2.0 mode as well as superspeed mode will be verified during USB 3.0 logo certification.

SuperSpeed USB uses dual simplex differential signaling operating at 5 GHz frequency to provide a 10x performance increase over high-speed USB. The higher power required to drive the 5 GHz signaling in superspeed mode is more than offset by the improved efficiency of 3.0 data transfers. The USB-IF estimates the system power necessary to complete a 20-MB superspeed data transfer will be 25% lower when compared with high-speed mode. This is possible because several architectural issues that hampered USB 2.0 power efficiency have been enhanced in the USB 3.0 specification below:

  • Elimination of device polling by allowing devices to asynchronously signal when they need service from the host.
  • The ability for device ports to initiate low-power states.
  • The ability for device ports to remove power from all or portions of their circuitry (function level suspend).
  • The ability to use data streaming for bulk transfers.
  • More efficient token/data/handshake sequence.
  • The addition of packet routing eliminates the need to broadcast packets to all endpoints downstream from hubs.

In addition to these changes, USB 3.0 improves efficiency by implementing power management at the link layer to provide greater speed and precision in managing power consumption. Figure 1 shows the power savings when using superspeed data transfer.


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Table 2 outlines the four power states in USB 3.0. Each state incrementally lowers power use while increasing the allowed exit latency. This method provides a more adaptive power-management model that uses timers and link-state awareness to reduce power use. Although the specifics of how devices will lower their power draw are left to the vendor, Table 2 outlines the link states defined by the USB 3.0 specification.


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Most early 3.0 devices rely on inactivity timers to initiate entry into the U1 state. In the U1 state, these devices will typically reduce power to their SuperSpeed PHY. These devices will progressively lower power to other parts of the interface as the inactively period increases. In some cases, host ports will immediately request transition to the most aggressive power suspend state (U3) during idle periods. This more rigid approach to lowering power draw is generally initiated by higher layers and is based on expected usage patterns for specific device classes. USB 3.0 also preserves function-suspend features from USB 2.0 allowing individual functions to be placed into a lower power state. The remainder of this article explores the SuperSpeed power-management model and the power-state transitions required by the USB 3.0 specification.
 Configure USB devices for power management
Four steps are involved in configuring a USB 3.0 device for power management.

  1. Devices must report their level of support for power management within their Endpoint Descriptors. While it's required for all devices to support power management to gain SuperSpeed certification, USB developers may elect to configure devices with this functionality disabled for specific applications.
  2. Host must send SET_FEATURE to U1/U2_ENABLE during configuration. Alternatively, some peripheral devices that are used intermittently may aggressively direct their own links to the lower power state. Higher layers require a mechanism to enable (or disable) the upstream port's ability to request low-power entry. When asserted, U1/U2_ENABLE allows the upstream port to initiate entry to U1/U2.
  3. Host must send Link Management Packet (LMP) to define the U1/U2 Inactivity Timeout. The U1/U2 inactivity timers allow the host to define the time interval between the U0 > U1 and the U1 > U2 power-state transitions. These timers provide the flexibility to delay power state transitions for specific applications, such as Blu-Ray disk writers, that could suffer usability problems if response latency is introduced. The U1 and U2 inactivity timeout can be as long as 127 µs and 65 ms respectively. Sending an LMP with the U1 inactivity timeout value between the range 0x01-0xFE also serves to implicitly enable the host port to initiate U1/U2 transitions.
  4. Host will inform the device of the U1/U2 System Exit Latency using SET_SEL. Reporting System Exit Latency (SEL) allows the host to more intelligently manage power state transitions for periodic endpoints, such as isochronous devices. SEL represents the total latency to transition the entire path of links between the device and host from U1/U2 back to U0. It provides a mechanism for higher layers to reduce or even disable U1/U2 entry if system exit latency exceeds the minimum service intervals reported by the device. Figure 2 shows a host-device exchange of Power Management Configuration data.


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Transitioning from U0 >U1
Either link partner can initiate a transition from U0 >U1 based on the expiration of the PORT_U1_TIMEOUT timer. Alternatively, some devices may attempt to save power by proactively initiating U1 mode more aggressively by setting their U1_Enable feature selector and reporting their U1 Inactivity Timeout equal to 0.

Initial entry into a low-power state is always negotiated between ports using the LGO_Un followed by LAU (accept) or LXU (reject). The port sending the LAU should wait until it receives a single LPMA (accept response), which serves as a final handshake before transitioning to any of the low-power states. To maximize power savings, ports are required to respond to power-management commands within the PM_LC_TIMER timeout. If the port initiating the state change does not receive an LAU or LXU before the PM_LC_TIMER expires (3 µs), it's considered a link error and should initiate recovery.

Alternatively, if after sending the LAU , the device doesn't receive the LPMA or any other valid traffic (such as TS1 , LFPS , Link Command ) before the PM_ENTRY_TIMER expires (6 µs), it should proceed to the low-power state anyway. In this event, it's assumed the LPMA was corrupted and the port issuing the LGO_U1 has already entered U1.Transitioning from U1 > U2
The transition from U1 to U2 is generally triggered by a second timer called the U2_Inactivity_Timer which, when enabled, will silently move the link to the lower power U2 state. This U2 inactivity time out value is reported by the endpoint's configuration descriptor. It's the host responsibility to enable this timer using the U2 Inactivity Timeout LMP. When a link enters U1, this starts the U2 inactivity timer and provides a mechanism for the port to autonomously move to the U2 state.

For some devices, it may not be practical for individual endpoint functions to enter U1 (in other words, composite devices that may have a shared PLL). Some devices may bypass the U1 mode altogether and instead transition the link from U0 directly to U2 using the LGO_U2 link command thus allowing a larger portion of the SuperSpeed interface to be suspended. A device can be configured to support U2 exclusively with SET_FEATURE: U1_DISABLE .

As mentioned previously, some devices may attempt to save more power by immediately transitioning to U1 or U2, using the U1/U2_Enable feature selector. For example, storage devices may immediately issue an LGO_U2 after each transfer if the packets pending bit is de-asserted in the previous transaction packet.

Transitioning from U0 > U3
The U3 state is a deep power-saving state where interface power may be removed. It's the equivalent of Suspend state in USB 2.0, and it can only be initiated by a downstream facing port using the LGO_U3 followed by LAU (accept). Upstream facing ports are not allowed to reject the LGO_U3 . While the goal is to conserve as much power as possible, while in U3, a port must still maintain its Warm Reset detect, U3 wake detect, (for host initiated wakeup) as well as wake transmission (for remote_wake capable devices).

Transitioning from U1/U2 >U0
Returning a link from U1 to U0 active state mandates the shortest recovery time in the range of 10 µs. This transition is normally initiated when a packet needs to be transmitted, such as an IN message from the host, or an ERDY message from the device. Ports in lower power states need a mechanism to signal its link partner to begin the link recovery process. Low Frequency Periodic Signaling (LFPS) is a 50-MHz side-band signal that provides a port with a low-power mechanism to send a “wake signal” to a link partner. Both sides must receive an LFPS “handshake” to avoid entering the Recovery link state before the far-end receiver is ready.

To deliver acceptable performance, SuperSpeed devices use a low-latency recovery sequence that provides a streamlined way to retrain links when exiting these low-power conditions. SuperSpeed ports may also enter the Recovery state when errors are detected during data transfers. In both cases, only TS1 and TS2 ordered sets are exchanged with the goal of returning the link to U0 as quickly as possible.

Resolving conflicts between commands
Numerous rules and conditions are defined in the USB 3.0 specification to preserve the integrity of the link during power-state changes. Included are obvious requirements such as disallowing devices from starting low-power transitions unless they have transmitted and received all pending data packets, acknowledgements, flow-control link commands, header and buffer credit advertisements. There are also rules to ensure links maintain coherency in the event an expected power-management response is not received.

For example, a port that sends U1 or U2 exit signal but does not receive an LFPS handshake from its link partner should transition to the SS.disabled state (assumes the sleeping device is removed from the system). Because power-state changes can be initiated by both host and peripheral device ports, several rules are designed to manage link-state race conditions and potential conflicts between ports. For example, peripheral devices that have sent an LGO_U1 or LGO_U2 and also received an LGO_U3 , should wait until they receive an LXU from the host and then send an LAU accept for the U3 request.

In the case of a host port that has been directed (by a higher layer) to initiate a transition to U3 while a transition to U1 or U2 has been initiated but not yet completed, the host port should complete the in-process transition to U1 or U2, then immediately return to U0 and request entry to U3.
Testing and verifying USB 3.0 power management
To ensure USB 3.0 devices properly implement these power management behaviors, they will be verified during the USB-IFs SuperSpeed certification program. Testing devices to ensure reliable operation in power-managed environments raises a substantial verification challenge. Post-silicon functional test teams may struggle to simply initiate power-management transitions as the necessary commands occur at the lowest layers making them difficult to control using software. Entrance and exit from these low-power states must occur within rigid predefined time limits. This task is greatly simplified by protocol-layer test tools that have the following capabilities:

  • Low-level traffic generation— To test many of the link states outlined above requires special test systems that can control and manipulate the logical link layer. Most functional test teams rely on traffic generators capable of emulating real device behaviors to perform this testing. These tools should be capable of creating intentional timing violations and invalid state transitions to test error recovery on the device-under-test. The ability to arbitrarily control link-layer handshaking in a consistent and repeatable way is important for validating power management and other USB 3.0 link layer behaviors.
  • Accurate capture of U1 recovery sequence— The SuperSpeed transition from U1 to the active state (Ux_EXIT_TIMER ) mandates both ports should enter U0 within 6 ms or the link will enter SS.disabled. Unlike Power-on link training, recovery from U1 uses a fast link-training sequence without the added equalization training symbols. This frequent retraining can occur in as little as 1µs, which places considerable pressure on analysis tools as they must seamlessly capture the LFPS handshaking and achieve 5-GHz signal lock during this shortened link-training sequence.
  • Triggering on power link-state changes— Traffic at the logical link layer is invisible to the upper layers of USB 3.0 protocol making it impossible to see Link Commands using software-based tools. This mandates using an inline protocol analyzer capable of accurately capturing link-layer traffic between devices. Triggering on link commands such as the LGO/LAU exchange and the LFPS wake signals are critical for efficient power management debug.  
  • Triggering on power-management timeouts— Returning to U0 from the U1 low-power state has proven to be a common problem area for early devices. This transition in particular can occur hundreds of times in only a few seconds. To minimize latency at the application layer, devices are required to enter and exit power save modes within very short timing windows. For example, during the low-power exit sequence, both link partners must exchange an LFPS exit handshake within 2 ms (tNoLFPSResponseTimeout ). If either side fails to send the required response, the opposite link will go to SS.disabled and the link should revert to USB 2.0 mode. Testing these behaviors is simplified if developers can set up independent event timers that trigger when either a handshake or the required state change is late. It's particularly useful to have a mechanism, such as that shown in Figure 3 , for capturing rare or intermittent timing violations during these power-management transitions.

  • Click on image to enlarge.


    Click on image to enlarge.

  • Monitoring VBUS power draw— VBUS power supplied by the downstream facing port can represent a significant source of battery drain for mobile platforms. Test equipment is now available that merges voltage meter functionality with protocol analyzer features. These systems, such as the one shown in Figure 4 by LeCroy, help users correlate actual VBUS power draw with protocol-layer state changes. These tools will typically display voltage graphically in a timeline format. This power information is synchronized to I/O requests, enabling users to correlate power use at the electrical layers with commands occurring at the higher layers.


Mike Micheletti
is the senior product marketing manager at LeCroy with over 10 years of experience defining high-speed serial data acquisition solutions for USB, WiMedia, Bluetooth, SAS, SATA, and Fibre Channel. Micheletti is a regular contributor to the USB-IF Compliance Working Group.

Further reading:
1.   Ethier, Sheridan. “Application-Driven Power Management,” 2004, QNX Software Systems Ltd.
2.   “Universal Serial Bus 3.0 Specification,” USB Implementers Forum Inc., 2008, www.usb.org.
3.   Walsh, James. “SuperSpeed USB Power Management,” 2008, www.usb.org.

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