This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
The industry expects IC-package developers to furnish more functionality and higher performance with each new generation of product offering. The trend of shrinking product sizes, increasing performance requirements and greater levels of integration continues unabated. In addition, supply-chain flexibility and the ever-present need to reduce cost are constant challenges that OEMs are facing.
These market requirements are driving on-going packaging innovation. For some time, two market trends have been evident. These are the need for increasing microprocessor speeds and the growing demand for additional functionality in electronic systems. In turn, these market trends are driving the demand for increased density and higher performance memory in systems such as high-end computers and servers.
To address these requirements, memory module manufacturers, in particular, are looking at technologies capable of meeting these dual demands while keeping overall costs down.
|Table 1. The market potential for multiple die memory packaging will not reach the same volumes as the traditional single die package, but the demand for higher density memory is significant.|
New generations of DRAM and double data rate (DDR) and DDR2 technologies are contributing significantly toward increased system performance. However, single-die packages cannot keep up with the demands of newer, high-end processor technologies.
The market potential for multiple die memory packaging will not reach the same volumes as the traditional single die package, but the demand for higher density memory is significant.
Although die-stacking is widely used in the silicon-packaging industry, many find that the effective stacking of components at the package level can offer many benefits for configuration flexibility. And because individual package layers in the stack can be fully tested prior to stacking, greater overall finished package yields can be assured.
The package- on-package (PoP) approach is increasingly being used to meet these needs and is rapidly becoming the engine for many new designs. The package outline is a “flange-type” BGA, whose body size or “outline” is typically de- fined without regarding a specific die size.
It is “flange-type” because the substrate or carrier of the package typically extends outward beyond the perimeter of the die, forming a flange-like extension with respect to the die. If many suppliers are qualified for the same die function, the substrate dimensions will likely be designed to accommodate the assembly of die with various sizes and won't be affected by any future die shrinks.
|Figure 1. A narrow rectangular slot opening in the substrate provides access for wire-bonding the memory die to the gold plated land features on the outer surface.|
The -Ball Stack package assembly is based on technology developed for the BGA package technology. In the assembly process, the dice are first placed (face-down) onto an elastomer attachment site furnished on the substrate base material and electrically interconnected through the slot feature using conventional wire-bond methodology.
After wire-bonding, the bond cavity is encapsulated to seal off the exposed bond window, which is then followed by the ball attachment process, electrical testing, marking and singulation. Testing of individual package units is also possible. However, many companies that are processing memory in high volume have found the strip-test process more efficient.
In preparation for package-stacking, the base or bottom packages are first transferred from their carrier-tray to a multiple unit alignment fixture. The actual stacking process begins with the transfer of the second-layer package to a dip-fluxing station to uniformly coat the bottom half of the ball-contact. With flux applied, the upper level packages are sequentially placed atop the base packages and repeated for each package layer before reflow soldering.
The loaded fixture is transferred to a forced air/gas convection oven for mass reflow to complete the interlayer solder joining of all package layers. Because of the relatively thin composite of elements within each section of the package, the overall height of the finished ZBall Stack package is minimized (ultimately determined by the number of packages joined in the stack).
Following a cleaning process and an electrical continuity test of the multiple pack age assembly, the Z-Ball Stack packages undergo a final physical inspection before transfer to partitioned trays for shipping to customer sites.
The two-die Z-Ball Stack package was the first member of this family of packages to be qualified and formally evaluated with environmental reliability testing, including mechanical, thermal and thermo-mechanical test regimes. Applications that require even greater stacking configurations have emerged.
The two- and four-layer memory package will likely have the strongest market appeal. Companies working on more specialized, high-end applications may even consider adapting the greater memory density made possible with eight-layer stacking. Memory products will generally require unique testing, grading, sorting and burn-in before the stacking process.
Ultimately, moving pre-packaged parts through all of the varied processes is far more efficient than attempting to test bare die, or to assume that all die within a multiple-die single package are functional.
Although these examples represent a stacked DRAM configuration, the ball-stack process is not exclusively reserved for memory applications. OEMs are discovering that any number of functions can be combined in this format including the mixing of logic, analog and other types of memory (baseband and flash, flash and SRAM or multiple flash-memory devices with a controller).
The test results for the Z-Ball Stack prove that it can furnish a practical low-risk solution for memory and mixed function, or for combining memory with logic devices. The Z-Ball Stack package has met industry-recognized thermal cycling requirements, and passed the drop and vibration test defined by OEMs.
Reliability experts are concerned that the higher process temperatures required for lead-free assembly may adversely impact product reliability resulting from acute material degradation. The combination of materials used for the assembly of the Z-Ball Stack package actually buffers the physical stress within the package by compensating for the CTE mismatch between the silicon die (3ppm/°C) and the laminate-based circuit board structure (15-17ppm/°C).
The primary benefit in multiple- die packaging is the increase in component density. The size and weight of the product will be reduced and functionality enhanced. This will be achieved through the integration of several device types. Other benefits include decreased circuit board complexity, improved product quality through higher reliability and reduced risk in getting the product to market. With multiple sourcing of already proven and mature die, time-to-market and cost-of-ownership can be minimized.
Vern Solberg is Senior Appl icat ions Engineer at Tessera Inc.