Use Cirrus Logic's CS556x/7x/8x ADCs to improve DNL and noise in control system designs -

Use Cirrus Logic’s CS556x/7x/8x ADCs to improve DNL and noise in control system designs

This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.

ADCs have long been a key element in the design and implementation ofcritical systems for scientific, industrial, medical and consumerapplications. With both product feature sets and performance demandsescalating relentlessly, designers are always looking for morecost-effective methods to achieve the desired measurement results fromtheir data converter circuits.

A widening range of complex designs such as ATE, medicalinstrumentation and monitoring devices, data acquisition systems,laboratory instruments and programmable logic controllers (PLCs) forindustrial automation, all depend on high-resolution ADCs to meetapplication objectives.

It is the ADC that provides the link between the “real world” ofanalog phenomena and the “processing world” that uses digitalinformation. The fundamental requirements for ADCs always revolvearound resolution, accuracy and bandwidth. Other importantconsiderations that must be considered in selecting an ADC aresignal-to-noise performance, distortion and latency.

Many applications need rapid responsiveness from ADCs to processhigh frequency or continuous readings from various sensors. The abilityto efficiently multiplex multiple signals within the ADC is becomingincreasingly important.

This is due to the growing requirement to handle multiple analoginputs within the same device, such as designing PLCs that are able tosimultaneously monitor and integrate real-time inputs from multiplesensors within a production environment.

Many conventional ADC architectures have inputs that presentdifficult drive requirements, demanding costly high-performance inputbuffers to deliver the needed responsiveness for continuous-processingscenarios.

Some ADC architectures even impose “mandatory quiet time” in whichthe system can't access the ADC's output during the sampling process,further complicating the design task.

Of course, other key considerations in any component selectioninclude the cost of the device itself and any support circuitryrequired to assure its proper functioning within the overall design.

This can be a particularly important issue with ADCs, especiallywhen used in a high-performance muxed environment because the requiredsupport circuitry can vary significantly depending on the type of ADCselected.

For example, if the ADC architecture doesn't inherently provide goodnoise rejection and measurement accuracy, it can require overdesigningthe circuit to meet performance goals.

Designs based on conventional successive approximation register(SAR) devices can present particular challenges because the boardspace, costs and power requirements associated with designing inputbuffers can quickly outweigh the apparent low-power specifications forthe SAR itself.

All of these factors play a critical role in the cost-effectiveachievement of design goals.

Traditional SAR approach
The types of high-performance applications mentioned have been designedaround ADCs using a SAR architecture, which provides a series of”snapshots” of the data at successive points in time. SARs havegenerally been targeted at applications that require fast response andlow latency.

However, because SARs are sensitive to noise and have relatively lowdynamic nonlinearity (DNL) performance, the need for significantsupport circuitry often drives up the overall cost and complexity ofSAR-based designs.

Poor linearity performance presents particularly challengingproblems because this error cannot be averaged out by oversampling ofthe signal. In too many cases, design engineers must compensate byoverspecifying the SAR and overdesigning the system to make up forSARs' poor DNL performance.

Similarly, the higher noise sensitivity of SARs and limitednoise-rejection capabilities present additional design challenges,especially in the inherently noisy environments for many deployments,such as PLCs on production floors or clusters of medicalinstrumentation in close proximity.

In contrast, ADCs using DeltaSigma architectures have traditionallybeen able to deliver improved DNL and noise performance, and allow formuch less complex support circuitry. DeltaSigma ADCs have notpreviously been considered appropriate for use in high-performanceapplications requiring low latency and high conversion rates to achievewide signal bandwidth. However, such “conventional wisdom” no longerholds true.

Cirrus Logic's CS556x/7x/8x family of high-throughput dataconverters consists of 16bit and 24bit ADC devices, and is built aroundan advanced DeltaSigma architecture that is designed to fully settle onevery conversion at rates of up to 200KSps.

This provides high-response, low-latency performance that iscomparable to SAR devices, making them suitable as cost-effectivealternatives in applications that traditionally required SARs. Alldevices in the product family are pin-compatible, enabling designers toproliferate a proven design into multiple product platforms withminimal redesign.

Figure1: (a) 'Sinc'-type filters are easy to implement, but they have tendedto be quite long and are thus slow to respond to a change in the input;(b) FIR-type filters are processed quickly and deliver a new outputword after only one sampling cycle.

Single-cycle latency
DeltaSigma ADCs have focused primarily on the highest-resolutionmeasurement of slow-changing signals such as those from temperaturesensors and weigh scale load cells.

Since noise rejection is critical to obtaining measurement accuracyin noisy digital environments, designers have already become accustomedto seeing long “sinc”- type digital filters that feature good rejectionof line frequency interference, such as 50Hz and 60Hz line frequenciesand their harmonics.

These filters are easy to implement, consume minimal die area andfeature good noise performance, but they have tended to be quite long(large number of conversion cycles needed to process the input signalbefore delivering an output word) and are thus slow to respond to achange in the input.

For example, Figure 1 above a shows the 3-conversion latency of the digital filter used in CS553x.The CS556x/7x/8x family incorporates a fast FIR-type filter that offerstwo advantages.

First, the filter is nearly flat to twice the sampling frequency,providing users with unrestricted frequency response, just as usershave come to expect from SAR-type converters. Second, the filter isprocessed quickly and delivers a new output word after only onesampling cycle (Figure 2b). This single-conversion latency allows thedevices to offer good noise and DNL performance such as in a DeltaSigmaADC with the high sample rate and Nyquist bandwidth of a SAR converter.

Another key advantage is the ability to overcome the “quiet period”imposed by many conventional SAR devices, in which the ADC outputcannot be accessed during certain parts of the sampling process.Testing of the CS556x/7x/8x family has shown that accessing the digitaloutputs at any time during the conversion cycle has no impact on theperformance of the device, including during full-speed operation.

Another SAR feature, convert on-demand, makes these devices suitablefor conducting asynchronous measurements that are often required inproduction environments. This allows for the ability to coordinateconversions with specific events, such as synchronizing flow withpulses or other sensor inputs.

In addition, true bipolar inputs are available when running bipolarsupplies. Current industry products run single-supply (+5V only) andrequire a level-shifter to move a bipolar signal up above ground, whichweigh down the system error budget with additional gain and offseterrors.

Buffered inputs
SAR-type converters present a challenge in analog signal inputs, wherethe designer must pay strict attention to component selection andcircuit layout to obtain the measurement accuracy specified for theconverter in the face of multiple noise sources.

Considering that the SAR converter itself can be a major noisegenerator due to the high-speed comparator used in SAR architecturesand the fast-changing digital circuitry within the device, this isoften a daunting task for even the most experienced system designers.

DeltaSigma converters offer inherent advantages that result insignificantly improved performance due to low sensitivity to noise andimproved accuracy. First, these devices provide integratedhigh-impedance input buffer amplifiers, which make it very easy toachieve the full specified performance without complex, expensiveexternal input buffer circuits.

SAR-based devices usually use sample-and-hold-type circuits tomaintain a stable representation of the sampled input signal during theconversion. As a result, the inputs of these devices usually present avery low impedance to the signal source, which usually includes a verylarge capacitance and requires an unusually robust amplifier circuit tomaintain a stable level at the input to the ADC during the dynamicsampling period.

This can be a challenging design task that demands buffer circuitsexceeding the cost and complexity of the remainder of the convertercircuit, as noise which is allowed to degrade the sampled input signaldirectly affects the accuracy of the conversion.

On the other hand, in some applications, high-throughputDeltaSigma-based devices can be driven directly from the sensor,without buffer amplifiers such as those required by conventional SARs.Second, since they oversample at the input, multiple samples (160samples in the case of the 24bit CS5560/1 devices, taken at an 8MHzrate), the low-pass filter provided within the DeltaSigma modulatorloop and the mathematical averaging performed within the digital filterreject or even ignore much of the noise that creates such significantproblems for SAR-based designs.

Another limitation often encountered in the current mixed signalenvironment is the single supply operation imposed by the use oflow-voltage submicron CMOS process technologies. The CS556x/7x/8xfamily offers bipolar analog input capability when operating from±2.5V supplies.

For users measuring ground-referred AC signals or transducers withnegative-going outputs this is a significant advantage, as the circuitneeded to shift a belowground signal to meet the input requirements ofthe single-supply converter requires a level-shifting amplifier thatintroduces additional noise and offset error to the sensitive low-levelsignal.

Figure2. One primary reason for the Delta Sigma device's better distortionperformance is the improved code-size uniformity due to better DNLperformance.

Distortion, DNL
Figure 2 above shows acomparison of the distortion performance for a widely used SAR deviceand the high-throughput DeltaSigma CS5571 device. The CS5571significantly outperformed the SAR device. At -12dB of FS, the SARexhibited a signal-distortion ratio of 91.6dB, while the CS5571 showeda 100dB S/D ratio.

One primary reason for the DeltaSigma device's better distortionperformance is the improved code-size uniformity due to better DNLperformance. DNL is basically the measure of code-width variation,normalized to full scale. It is the deviation from a uniform or meancode size, which results in one code size representing a differentvoltage step size than another code.

DNL plots such as Figure 3 below provide a clear visual representation of variations in code size thatcontribute to missing codes, gain and offset errors. The SAR DNL plot,measured from a leading SAR device, shows a wide variation in codesize, while the accompanying CS5571 DNL plot shows significantly lowererror across the entire input range while running at the sameconversion speed.

Figure3: DNL plots provide a clear visual representation of variations incode size that contribute to missing codes, gain and offset errors

Typical scenarios
This combination of high resolution and unrestricted signal bandwidthallows designers to perform noise processing and filtering of signalsthat are tailored to their specific application requirements. Whereapplicable, this could even include adaptive filtering, offering newcapabilities that have previously been unavailable for high-resolutionmeasurement applications.

One of the most exciting application areas that will be positivelyimpacted by this new technology is the design of embedded capabilitiesfor PLCs and process control systems.

Over recent years, industrial automation environments have beenmoving toward a greater emphasis on decentralized control, usingcompact, multifunction solutions that can be adapted to handle avariety of real-time sensor inputs along with embedded intelligence andclosed-loop responsiveness for implementing local decision loops.

In too many cases, the poor DNL performance, noise characteristicsand the need for additional support circuitry have limited theusability of SARs for implementing nextgeneration modular PLCs.

High-throughput DeltaSigma devices overcome these hurdles, making itpossible for designers of PLCs to build in high resolution and lowlatency while maintaining high measurement accuracy with a consistentlevel of DNL performance. This is particularly important for real-timeclosed loop applications where it is critical to maintain “no missingcode” performance and avoid steps in the transfer function of the ADCthat could result in “undefined” conditions in the control loop.

ATE represents another key application area in which multiplesimultaneous input streams must often be monitored and processed inreal time. Here, consistent DNL performance is essential for achievingaccurate test results, especially when continuously monitoring testinformation over an extended period of time while watching for smalland sometimes subtle signal variations.

Also, for some ATE systems used to test and measure noisesensitivedevices, the inherent noise sensitivity of SARs could present anadditional challenge by actually interfering with accurate testresults.

As mentioned above, designers often resort to using SAR-typeconverters with significantly higher resolution or speed than theyreally need, and average multiple samples in an attempt to get thedesired system measurement accuracy.

DeltaSigma converters, on the other hand, can be depended upon todeliver full accuracy with every reading, thus avoiding the need forexcessive resolution or sampling rates and the post processing ofless-than optimal results. In the ATE realm, this results in higherthroughput, which equates directly with lower test costs for the endcustomer.

ATE applications also represent an area in which the adaptivefiltering possibilities can allow test parameters to be dynamicallyadjusted during the testing process.

Medical instrumentation is another important market segment that canbenefit from high throughput data converters. Devices such as bedsidemonitors, blood analyzers and other diagnostic systems havetraditionally used 12-16bit ADCs, but many designers of these deviceshave already recognized the potential advantages of transitioning tohigher-resolution devices.

This will enable them to digitize a transducer signal directly andthen to perform signal gain and offset corrections in software, thusimproving both accuracy and analytic flexibility. The availability ofnew high-throughput DeltaSigma devices in a pin-compatible family of16bit and 24bit offerings means that medical device designers can nowmake a smooth transition to higher resolution without the risks ofrunning into a dead-end or compromising future flexibility.

Weighing scales represent another key application arena, in whichthe need for highly accurate continuous measurements provides a vitalrole for implementing precision batch control and high-speed weighingfunctions.

The actual production output can span a diverse range, from heavybulk products such as concrete to consumer products such as potatochips. However, the need for accuracy and fast response is critical toachieving quality and throughput goals. For example, weighing scalesused in processing bags of potato chips must be able to provideweighing accuracy to +.01oz for sustained processing speeds as high as3-5 bags per second.

The advanced approach of this data converter architecture addressesthe fundamental objectives of high resolution, low latency and highsample rate. Support for applications with continuous samplingrequirements can be provided without either requiring large inputbuffers and complex support circuitry or imposing undue restrictions onaccessing the devices' output buffer.

Rich Wegner is Senior Marketing Manager at Cirrus Logic Inc.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.