Use new DRAM advancements to push embedded systems performance higher - Embedded.com

Use new DRAM advancements to push embedded systems performance higher

For mainstream memory, the road is well-mapped and traveled. Fromfast-page (FP) mode and extended data out (EDO) to SDR, DDR and DDR2,the evolution has brought advanced architectures, faster speeds, higherdensities and bandwidths, and lower supply voltages and powerconsumption. These significant advancements have combined to advanceDRAM – and the computing market segments – to even higher performancelevels.

Advancements in DRAM technology have been accompanied by theemergence of multicore processors, new operating systems, andincreasingly divergent requirements across many different computingplatforms and applications (e.g. servers, workstations, mass storagesystems, supercomputers, PCs and peripherals). With each transitionfrom one generation of memory to the next, memory considerations havebecome more complex.

The transition to DDR3 is no exception. But with a clearunderstanding of how main memory has evolved and the trade-offs thathave occurred, designers can choose the high-performance memory devicethat best meets the needs of their platform, OS and application.

Before DDR technology, there was SDR technology. And before SDR,there was FP/EDO memory, where data is transferred asynchronously, sothat there is no clock signal that data/address/ command signals arereferenced to. SDR technology improved this by providing a clock inputthat these signals are referenced to, and data is transferred on therising edge of the clock (low-to-high transition).

Table:DDR3 takes off where DDR2 leaves off.

With the use of a DRAM clock pin that is synchronized to the systemclock, much higher data rates are achieved than is possible withasynchronous memory.

In 2000, DDR SDRAM was introduced to the market. DDR technologydoubles SDR data rate by transferring data on both the rising andfalling edges of a clock cycle. With DDR, 2bits (per data line) aretransferred every clock cycle (rather than the 1bit with SDR).

To do this, 2bits are accessed from the memory array for each dataline on every clock cycle. This process is called the 2-word or2n-prefetch (The core clock cyclehere refers to the cycle time of the memory array, and the frequency ofthe memory array is half that of the I/O buffer and one-fourth of thedata rates .). Prefetch helps get speed at an evolutionary pace,improving yields and increasing performance.

DDR2 SDRAM functions much like DDR SDRAM, but with new features thatenable faster speeds, and DDR3 takes off where DDR2 leaves off.

While DDR has a 2nprefetch and DDR2 a 4n-prefetch, DDR3 has an8n-prefetch. DDR3's internal data cycle time is one-eighth of theexternal clock rate, and the internal data bus width is 8x the size ofthe external data bus width. With DDR3, 8bits of data are moved fromthe memory array to the I/O buffer per data line on each core clockcycle.

Other bandwidth-enhancing features include lower RTT (terminationresistance) values to support higher data rates. DDR2 values start at50 ohms, while DDR3 values start at 20 ohms.

DDR3 offers an array of technological improvements that emphasizefaster speeds and improved performance. DDR3 devices are designed forhigh-speed signaling. An improved pinout with more power and groundballs provides better power delivery.

Improved distribution of power and groundballs combines withimproved signal referencing to enhance signal quality. The DDR3 D/Qarray lessens D/Q skew and tightens D/Q timing. A fully populated ballgrid improves mechanical reliability.

Because DDR3 has twice the bandwidth of DDR2, DDR3 speeds pick upwhere DDR2 leaves off. DDR3 speeds start at 800Mbps and max out at1,600Mbps. When a 64bit bus bandwidth is figured in, DDR3 hits speedsof 6,400- 12,800 Mtransfers/s.

The supply voltage for DDR3 has been reduced to 1.5V, a decrease ofjust under 20 percent compared to standard 1.8V DDR2. This isparticularly important for lower data rate applications like mobilecomputing. A 15-20 percent power savings in mobile computingapplications, where power is valued over performance, is significant.The low power consumption of DDR3 will be similarly advantageous tonotebook applications.

DDR3's 34 ohm driver, compared with DDR2's 18 ohm driver, isoptimized for two modules per channel and point-to-point systems. DDR3SDRAM drivers have also been enhanced with capacitance reduction,dynamic on-die termination (ODT) and a new calibration scheme.

To reduce the input capacitance of a combination outputdriver/termination driver, DDR3 implements a merged driver. This driverenables multiple termination values, using combinations of the samepull-up and pulldown driver structures.

In fact, the most significant advantage of a merged driver is itsability to reduce capacitance by reusing these structures – a keydistinction from DDR2, which uses separate structures for the outputdriver and termination driver impedance.

New characteristics
DDR3's new, dynamic ODT feature has the flexibility to optimizetermination values for different loading conditions, which improvessignal integrity.

It also provides a way to manage the termination power consumption.Dynamic ODT enables a DDR3 device to change termination valuesseamlessly between write commands issued to different modules. This isa feature not available with DDR2 systems, which require bus idle timeto change termination values on the same device.

Master reset is a new DDR3 feature. This function improves systemstability by eliminating unknown startup states, and ensuring knowninitialization and recovery states. This removes the burden on thecontroller to ensure that no illegal commands are given.

This new function clears all state information in the DDR3 memorydevice without having to individually reset each control register orpower-down the device. This saves time and power when bringing thedevice to a known state. The DDR3 reset works on cold and warmboot-ups.

DDR3 is initially targeted at computing and graphics-intensiveapplications, such as high-end desktop PCs and workstations where vastamounts of information must be processed to create life-like images foran enhanced user experience. Its additive and write latency schemeswill also improve command bus efficiency in server applications.

DDR3 demand in that segment will likely begin to grow next year.Notebook demand for DDR3 is also expected to accelerate next year,primarily because of its lower system power demand.

Demand for DDR3 in other applications, such as networking and DTV,is expected to increase in 2010.

Kevin Kilbuck is Senior Segment Marketing Manager at Micron Technology Inc.

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