Use power delivery system analysis to improve design power/performance characteristics -

Use power delivery system analysis to improve design power/performance characteristics


Power delivery system (PDS) analysis and design have becomeincreasingly important in the communication, networking and consumerelectronics industries.

In the International TechnologyRoadmap for Semiconductors, IC power supply voltagecontinues todrop with the inevitable scaling of VLSI technology. The migration from130nm to 90nm has shrunk supply voltages to 1.2V and below, andconsiderably increased currents supplied to devices through the PDS (Figure 1, below ).

Figure1: The migration from 130nm to 90nm has shrunk supply voltages to 1.2Vand below, and increased currents supplied to devices through the PDS.

These developments pose challenges to PDS design – from DC IR dropto AC dynamic voltage fluctuation control – especially as margins gettighter.

A PDS used in high-speed design can be divided into three sections:silicon (on-chip), IC package and printedcircuit board (PCB), shown inFigure 2, below . The on-chip power-grid structure containsseveral metal layers with either x or y direction power and groundrails. Vias are used to connect the rails sitting on different metallayers.

Figure2: A PDS can be divided into three physical sections: silicon, ICpackage and PCB.

For high-performance chips, there are integrated decoupling cellsfor both core and I/O powers. Like a small PCB, an IC package can haveseveral power and ground plane layers with complex shapes. There arealso on-package decoupling sites reserved for small capacitors.

The PCB usually has more well defined solid power and ground planes,large and small discrete caps, and a voltage regulator module. Wirebonds, C4 bumps and solder balls connect the silicon, package andboard. The entire PDS must ensure stable voltages in multiple powerdomains for power to reach the IC devices at a nominal level.

However, there will always be noise induced by switching currentsand frequency- dependent distributed parasitics inherent in PDS. Thevoltage variation can be estimated by the equation DeltaV = Z x DeltaI, where Delta Vis the voltage fluctuation that appears at device end and Delta I istheswitching current. Z is the power ground input impedance looking intothe entire PDS at the device end. To reduce voltage variations, the PDSmust have very low impedance.

At DC, such low impedance reflects a low IR drop for the powersupply; at AC, such low impedance provides low transient noisegenerated by switching currents. PDS and signal distribution system areclosely related since power and ground serve as signal return paths andreference planes.

DC IR drop
Much attention has been given to on-chip IR drop inview of the severeresistive loss caused by the small size (a few microns and below) ofthe chip power grid. Board-level IR drop (in the range of tens tohundreds of millivolts) can have a significant impact onhigh-performance designs if you:

1) Always check your boardfor “Swiss-cheese” effect, neck-down and dynamic plane cut (Figure 3, below ).

2) Worry about insufficientpin, via, ball, bump, copper weight for the current paths, or theimbalance of these current paths.

3) Design a low-voltageand/or high-current product that has difficulty meeting the voltagedrop margin.

Figure3: Common physical designs increase current path resistances at PCBlevel.

For example, higher-density, high-pin-count components have largevia fields, and their associated anti-pads create a Swiss-cheese effecton the power distribution layers of both IC packages and PCBs. Thiseffect creates a smaller equivalent conductor of higher resistance.Given the high impedance path of the PDS, insufficient power might bedelivered to some devices on the PCB.

A good DC IR drop simulation is thus needed to estimate the voltagemargin of PDS. Furthermore, through various what-if analyses, it canhelp formulate design solutions or guidelines during the preandpost-layout stages. Layout, system, SI and power engineers can also useIR drop analysis as a sign-off tool for design rule checking (DRC) forevery power and ground net on all boards, with a comprehensive IR dropconstraint manager. This flow can minimize layout issues on complex PDSgeometries, which can only be identi- fied by an automated softwaresolution.

Figure4: IR drop analyses can pinpoint critical voltage and currentdistribution in the PDS for a high-performance PCB.

Figure 4 abov e shows that IRdrop analyses can pinpoint critical voltage and current distribution inthe PDS for a high-performance PCB.

Impedance analysis
Most people equate a pair of metal planes with a parallel platecapacitor.Planes actually provide the “plane capacitance” that helpsmaintain power-supply voltage stability. At low frequency, when thewavelength is much larger than the plane dimension, the pair of planesdoes indeed behave as a capacitor.

However, as frequency increases, the planes' characteristics becomemuch more complex. More precisely, a pair of planes forms a parallel-plate transmission-line system. Power and ground noise, or thecorresponding electromagnetic fields, spread through and follow therules of the parallel-plate transmission-line system.

When the noise wave spreads and reaches the edges of the planes, asmall portion of the high frequency energy will radiate, but the largerpart of the energy will bounce back. Multiple reflections fromdifferent edges of the planes cause the resonance inside the PCB.

Figure5: Shown is the input impedance of a pair of planes as compared withthe impedance of a pure capacitor and pure inductor.

Resonance inside the PCB is a distinct phenomenon in AC power andground impedance analysis. Figure 5above shows the input impedance of a pair of planes as comparedwith the impedance of a pure capacitor and pure inductor. The planesize is about 30cm x 20cm with about 100µm plane separation andfilled up with FR4 material.

The plane capacitance is about 20.9 nF, and avoltage regulator moduele (VRM )mounted on boardis modeled as a 3 nH inductor. One can see that the planes (withoutVRM, red curve )behave as a capacitor up to tens of MHz (tracking theblue curve ,value going down).

Above 100MHz, the impedance of the plane is mostly inductive (valuegoing up and tracking the green curve ).At hundreds of MHz range, anumber of peaks corresponding to the resonant behavior start to appear,showing the plane is no longer purely inductive.

By now, it is clear that a low-impedance PDS (from DC to AC) isessential for low voltage fluctuation. The design goal for PDS alsogets clearer: to reduce inductive effect, enhance capacitive effect andremove/reduce high-value resonance peaks. To reduce PDS impedance, thefollowing design practices may be applied:

1 . Reduce the distancebetween the power and ground planes.
2. Make the planes bigger.
3. Increase the dielectricconstant of the material between planes.
4. Add more power and groundplane pairs.

Due to manufacturing and other design considerations, however,designers often need other methods and greater flexibility to reducePDS impedance. Adding discrete decoupling capacitors on board is a goodalternative, especially in removing resonance peaks within specificfrequency ranges.

Figure6: Shown is the input impedance of a PDS simulated by Sigrity PowerSIwith three different scenarios.

Figure 6 above shows theinput impedance of a PDS simulated by Sigrity PowerSI with threedifferent scenarios:

a) Without VRM modeled,without any decoupling capacitors mounted on board
b) With VRM modeled as a shortcircuit, without any decoupling capacitors mounted
c) With VRM modeled as a shortcircuit, with some decoupling capacitors mounted

In the first scenario (blue line ),the PDS input impedance observedat the IC-chip location shows a capacitive behavior at low frequency.As frequency increases, the first natural resonant peak shows up at800MHz, corresponding to the physical size of the power ground planes.

In the second scenario (green line ),the input impedance appears tobe inductive at low frequency, which corresponds to the loop inductancefrom the IC-chip location to the VRM location. This loop inductance andthe plane capacitance together induce a resonant peak at around 200MHz.

In the third scenario (red line ),with decoupling capacitors mountedon board, the 200MHz resonant peak is pushed to a much lower frequencyrange (< 20MHz).

With a much lower amplitude, the first strong resonant peak nowappears at about 1GHz. This plot illustrates that, by adding decouplingcapacitors, PDS achieved low and smooth AC impedance response withinthe major operating spectrum. Low PDS noise can therefore be expected.

The addition of decoupling capacitors gives an engineer theflexibility to tune the PDS impedance and consequently achieve lowpower ground noise. However, design issues, such as where to placedecou pling capacitors, how many should be placed on the board, whattype of capacitors should be used, are sure to emerge. Extensive PDSsimulations using the right tools are necessary to determine aneffective decoupling strategy for a particular design.

Co-design concept
Show in Figure 6 above is anillustration of a very important fact: on-board decoupling capacitorscan only cover frequency range of up to several hundreds of MHz. Beyondthat, the parasitic inductance associated with each discrete decouplingcapacitor will greatly reduce the decoupling effect. PDS impedancecannot be further reduced just by board level capacitors.

Figure7: The graph shows input impedance simulation results with differentconfigurations.

From several hundreds of MHz and beyond, package PDS capacitance andon-package discrete decoupling capacitors come into play. And forgigahertz range decoupling needs, on-chip power grid capacitance andon-chip decoupling capacitors are the only answer. Figure 7 above shows the  threecases.The red line represents the input impedance of a board with somedecoupling capacitors.

The first resonant peak is around 600MHz to 700MHz. After a packageis added into the model, the extra package inductance causes theresonant peak to reach around 450MHz as shown by the blue line .

Then after adding the chip model, the high-frequency resonant peaksare eliminated by the on-chip capacitance; but a very low and weakresonance is introduced at the 30MHz range as shown by the green line. This 30MHz resonance peak will manifest in the time domain voltagedroop as the middle frequency envelope of the high frequency switchingwaveform.

On-chip decoupling is effective, but it consumes precious siliconreal estate and leakage current. Moving certain onchip capacitance topackage level could be a good design compromise, but it requiressystem-level knowledge from chip, package to board.

Typical board-level engineers may not have access to such designdata and simulation tools while IC designers usually don't care muchabout downstream package and board designs. But it is clear that asystem-level approach involving co-design of chip-package and packageboard will be the future trend in PCB design and analysis.

Jin Zhao isSenior Technical Staff Member, and Raymond Chen is Vice President at Sigrity Inc.

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