Using ADC sampling capacitor structures to control system level voltage surges - Embedded.com

Using ADC sampling capacitor structures to control system level voltage surges

Today's analog system designers face many design challenges. Not onlydo designers need to select the proper IC components, but they mustalso accurately predict the interactions of these components within thesystem.

ADCs can pose an especially difficult challenge in this regard,offering a variety of different input sampling architectures that mustbe considered on the system level.

This article will explore several common types of input samplingarchitectures and discuss the implications each model has on the restof the system.

A common solution found in many current CMOS ADCs is the use of aswitched-capacitor structure to accomplish input sampling. In its mostbasic form, this input structure is composed of a relatively smallcapacitor and analog switches.

Figure1: A common solution in current CMOS ADCs is the use of a switchedcapacitor structure.

When the switches are configured in position 1, the samplingcapacitor is charged to the voltage of the sampling node, in this case VS .The switches are then flipped to position 2, where the accumulatedcharge on the sampling capacitor is transferred to the rest of thesampling circuitry. The process then begins all over again.

System-level issues
An unbuffered switched-capacitor input can cause significantsystem-level issues. For example, the current required to charge thesampling capacitor to the appropriate voltage must be supplied from theexternal circuitry connected to the ADC input.

When the capacitor is switched to the sampling node, a large amountof current is required to begin charging the capacitor. The magnitudeof this instantaneous current is a function of the size of the samplingcapacitor, the frequency at which the capacitor is switched and thevoltage present on the sampling node.

Figure2: A resistor in the ADC provides sensor isolation and improves ESDprotection.

This switching current is described by the equation: Iin = CVf , where C is thecapacitance of the sampling capacitor, V is the voltage present on thesampling node and f is thefrequency at which the sampling switch is turned on and off. Thisswitching current results in high current spikes on the sampling node.

The implications of this switching current must be considered whendesigning the analog circuitry in front of the ADC. As this currentpasses through any resistance, a voltage drop will occur, resulting ina voltage error at the sampling node of the ADC. The error can becomesubstantial if a high-impedance sensor or filter is connected to theinput of the converter. Assume that a resistor is placed in front ofthe ADC to provide sensor isolation and improve ESD protection.

Figure3: The sampling capacitor is charged or discharged such that thevoltage on the capacitor is equal to the voltage at the sampling node.

In this example, the sampling capacitor is 10 pF and is beingswitched at 1MHz. Using the equation above, the instantaneous currentis approximately 25 microAmperes. As this instantaneous current passesthrough the 10 kilo-ohms resistor, an error voltage of 250mV will occuron the sampling node. This is a worst-case approximation, as thesampling node may settle prior to the next sample cycle.

This settling time is dependent on the RC time constant formed bythe 10 kilo-ohm resistor and the sampling capacitor, plus any parasiticcapacitance on the input of the ADC. Parasitic capacitance can be dueto the leads of the ADC, trace lengths on the circuit board andinternal MOS switch capacitance.

An external buffer circuit may be required to supply the neededcurrent and ensure that the sampling node is properly settled tomaintain linearity.

However, the amplifier output impedance will increase at higherswitching frequencies. Care must be taken when selecting the amplifierand associated circuitry to account for this instantaneous switchingcurrent.

Figure4: Regardless of the sampling architecture, ADCs must implement ESDprotection.

Minimizing instantaneous current
An internal buffer can be implemented to minimize the instantaneouscurrent requirements of the external circuitry. In this implementation,the analog switches combine to form three different states. In position1, the sampling capacitor is quickly charged to the sampling nodevoltage, plus or minus the buffer offset.

The instantaneous current required to charge the capacitor duringthis phase is provided by the internal buffer circuitry. The internalbuffer can be optimally designed to provide a low-impedance output atthe required switching frequency that can properly charge the capacitorin the allotted time.

The switches are then reconfigured to create a connection atposition 2. During this phase, the sampling capacitor is directlyconnected to the sampling node of the ADC.

The sampling capacitor is then charged or discharged such that thevoltage on the capacitor is equal to the voltage at the sampling node.Some switching current may still be present, but less current will berequired from the external circuitry, since the capacitor voltage isalready charged to within the offset voltage of the internal buffer.

Finally, the analog switches are configured to position 3, allowingthe sampled voltage to be transferred to the rest of the samplingcircuitry. The advantage of a buffered switched-capacitor input is asignificant reduction in the instantaneous current required from thecircuitry external to the ADC. In the earlier example, the samplingcapacitor is 10 pF and the switching frequency is 1MHz.

Assuming the internal buffer has an offset of 10mV, this wouldresult in an instantaneous current of only 100nA – 250 times less thanthe instantaneous current in the unbuffered sampling input.

In some cases, a fixed or programmable gain amplifier is integratedinto the same silicon in front of the ADC. The amplifier not only helpsto reduce the switching current that must be supplied by the externalcircuitry but also provides amplification of the analog signal.

A chopper- stabilized amplifier can also be implemented to reducethe 1/f noise, sometimes referred to as “flicker noise.” This lowfrequency noise is due to the surface states in the channel of the MOStransistors inherent to the process technology. Chopping can remove the1/f noise and reduce the external current requirements. However, someinput instantaneous current would still be seen due to mismatches inthe MOS switches.

Regardless of the sampling architecture, ADCs must implement someform of ESD protection. For CMOS solutions, this protection typicallytakes the form of clamping diodes.

These clamping diodes effectively limit the voltage that can beplaced on the transistors internal to the converter. If the inputvoltage goes above or below the supply rails by more than a diode drop(typically 0.7V), the diode will begin to conduct current and limit thevoltage.

However, these clamping diodes also exhibit current leakage, whichmust be considered when designing the analog input circuitry. Althoughthis leakage current is typically small, the current can increase as afunction of temperature.

Kevin Tretter is Senior ProductMarketing Engineer, Analog and Interface Products Division at MicrochipTechnology Inc. To read a PDFversion of this story, go to “ Keyin sampling architectures in ADCs.” 

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