Using chip-on-chip SiP techniques in small footprint embedded designs -

Using chip-on-chip SiP techniques in small footprint embedded designs

The soaring popularity of cellphones and digital still cameras (DSCs)requiring small-form-factor IC packages has spurred considerableinterest in system-in-package(SiP) solutions. But SiP isn't just about size.

Because each functional chip can be developed individually, SiPmeans faster development and lower cost as compared with SoC , which must be developed as onelarge single-chip design.

As early as 2001, SiP solutions were already being built fromfunctional chips that have been qualified, designed and intended forsingle-chip packages.

SiP and chip-scale packaging
Essentially designed for chip-scale packaging, thesesolutions posed a big problem to SiP development: when two chips werestacked, their pads cannot be aligned. Sometimes, the correspondingpads are located on opposite sides of chips, thus requiring signalrouting over the interposer.

Connections available with multilayer package interposers havedrawbacks, as wires became longer and signal integrity (SI)deteriorated. In addition, package interposer costs increased.

To avoid such disadvantages, design engineers developed SiP chipswith pad locations that fit shorter wire connections. For example,memory interface pads are put on the top and bottom, and signal padsthat connect to the outer pins are put on the right and left sides ofthe logic chip.

If the memory chip is rectangular, pads are moved to the shortersides of the rectangle. The logic chip and the memory chip are thenstacked in one direction, connecting the memory chip's shorter linewith the logic chip's top and bottom, which have the memory interfacepads.

Side-by Side SiP
On the other hand, side-by-side SiP packaging is widely used whencombining chips from different wafer processes and generations isneeded. For example, a side-by-side SiP in an automotive applicationmight include a signal processor chip made from a logic waferfabrication process and an actual driver chip made from an analog waferfabrication process.

In that case, performance and cost of the signal processor could beimproved using a new-generation wafer process, while the driver chipwould remain in its stable wafer process due to the 12V handling andendurance requirement.

Since new-generation processes cannot handle higher voltages, an SiPapproach becomes the prime candidate for this combination. Packagingsolutions with both analog and digital functions pose another problem.

If an analog chip includes the signal input receiver or outputdriver functions, then the signal, amplitude and polarity arecontrolled first by the digital chip and then through the analog chip.This combination is always a series connection, and usually the analogchip is smaller than the digital chip.

If these combinations assumed a stacked-chip structure, then theanalog chip would be put on top of the digital chip. The signal wouldstart from the digital chip pads. It would pass through the analogchip, through the signal wire connecting the package interposer, andthen route over both the analog and digital chips. A better selectionwould be a side-by-side SiP.

Figure1. A CoC approach with bump connections instead of gold wireconnections has been developed to meet the needs of mobile devices.

Chip-on-chip SiP designs
Side-by-side SiP solutions used to look very much like miniaturemultichip modules, butperformance improvements of the original singlechip required the addition of subchips. The idea of stacking chips inan SiP came about as a way to decrease the total footprint.

Take DSCs as an example of a recent application that demands bothhigh performance and small size. Current models usually have a 5M pixelsensor. A couple of years ago, sensors were typically 1M pixel, whichmeans that a fivefold increase in performance was required. Moreover,power dissipation needed to be reduced to ensure the longer batterylife essential for today's DSCs.

To satisfy these opposing requirements, companies developed achip-on-chip (CoC) approach that has bump connections (Figure 1, above ) instead ofgold-wire connections between the logic and memory chips. Because thereis no gold wire between the logic chip and memory, the signal datatransfer rate is higher.

The CoC approach also dissipates less power and has a dedicated I/Obuffer. A general double-data-rate memory bus requires a 2.5V signalswing, 5mA maximum current and 125mW maximum power per signal pad. Whenthe dedicated I/O buffer is applied, a 1.2V signal swing – the same asa conventional 130nm power supply – becomes a suitable option.

Since the I/O buffer load is just a point-to-point connection,one-tenth current can be applied. As a result, operating frequencyincreases five times, at half the voltage, one-tenth the current andone-fourth the power. One additional benefit is a smaller chip size.

With newer-generation wafer processes for logic chips on the riseand requests for more memory capacity increasing, memory chip sizeseems to be exceeding logic chip size. This means that there is noexposed pad area to make a connection for the outer pin.

The Association of Super-Advanced ElectronicsTechnologies has described a 3D through-hole stackedstructure that can address this problem. With this technology, smalllogic chips can handle large memory capacity without SI degradationbecause of the short path between the logic chip and the stacked memorychips in the 3D through-hole substrate.

Development in this area has just begun and new avenues forexploration are abundant. For instance, a designer could choose a logicchip with the same size as a memory chip and stack it along with memorychips using a 3D through-hole substrate. Byrepeating the logic chip and stacked-memory chip structure, thedesigner could eventually produce an SiP with “huge-scale” memory.

SiP solutions come in several shapes, including stacked-chipstructures that target small for m factors, side-by-side solutions forI/O terminal functional chips, CoCs for high-frequency operation usinglow power, and 3D through-hole stacked structures for large memorydevices.

The main benefit of an SiP had been its short development lead time,but feasibility studies have shown that SiPs can perform like SoCs. Inaddition, SiPs allow the combination of different wafer process chipsin one solution, making them not only a package, but also a truesystem.

Mamoru Kajihara and Han Park aresenior packaging engineering managers at NEC Electronics America Inc.

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