Using clock generators/buffers to adapt your PCIe design to specific application needs -

Using clock generators/buffers to adapt your PCIe design to specific application needs

The PCI Express (PCIe) interconnect has grown popular over the past five years and is now widely used in many different markets and applications. Originally developed for use in the personal computing (PC) and server markets, the PCIe standard has become a de facto data bus used in communications, storage, industrial, and consumer electronics products.

Although the performance requirements for PCIe reference clocks are standard within any application, numerous clock generator and buffer products optimized for PCIe are available to help systems designers address the unique requirements of consumer, server/storage, and communications applications.

A PCIe data link (Figure 1 ) consists of one or more lanes encompassing a transmit (Tx) and receive (Rx) differential pair. A PCIe slot may contain up to 32 lanes, providing excellent bandwidth scalability. The first-generation PCIe specification was introduced by the PCI-Special Interest Group (SIG) in 2003, with a maximum data throughput of 16 GBytes per second (GB/s) in a 32-lane configuration. At the time, this specification was a major improvement over the previously used PCI and PCI-X bus architectures. Four years later, the PCIe 2.0 spec was released, which doubled the transfer rate to 32GB/s in a 32-lane configuration. This effectively meant designers could get the same amount of data transfer bandwidth in half the lanes of a Gen1 based design. The PCI-SIG introduced the third-generation specification in November 2011, again doubling the transfer rate to 64 GB/s.

Figure 1: The PCI Express Link

Market trends fueling PCIe adoption
In 2007, PCIe Gen2 had become widely used in most server/storage and communications infrastructure applications. At the same time, PCIe Gen1 started gaining traction in the embedded, instrumentation, and customer premises equipment (CPE) markets. The need for higher data throughput, an attractive cost point, scalability, and growing availability of PCIe ports in SoCs, ASICs, microprocessors, and FPGAs were all contributing factors in PCIe Gen1 proliferation into these markets. Multi-function printers, network switches, routers, wireless access points, and high-end consumer electronics were all starting to adopt PCIe as larger amounts of digital data were being created and used by consumers.

Although the consumer electronics market had not yet adopted the PCIe interconnect, it was fueling the requirement for PCIe to continue scaling towards higher data rates and larger bandwidth capability. By early 2008, smartphone adoption and social media were both rapidly growing in popularity, enabling end users to not only create, store, and share new digital media content such as pictures and video but also to request access to that content anywhere and anytime via the Internet and cellular devices.

At the same time, cloud computing and audio/video streaming services were becoming popular with consumers. Furthermore, Internet-based high-definition music and video services were becoming mainstream, increasing demand for higher bandwidth capability from server and datacenter infrastructure. Consumer thirst for high-resolution media content was requiring more bandwidth at faster speeds.

These market trends led to the adoption of the PCIe Gen3 interconnect standard, which has been predominantly used in server, storage, and datacenter end markets to date. New technology advancements in solid state drive (SSD) devices have further enabled datacenter and cloud computing to keep up with consumer demand for digital content. Enterprise SSDs use PCIe Gen3 as the main interconnect between the host motherboard and SSD controllers, enabling incredibly fast access to content stored in datacenters and in the cloud.

By using PCIe Gen3, networking and enterprise equipment manufacturers have been able to scale bandwidth and data rates without rebuilding the entire infrastructure. As with the previous generation shift from PCIe Gen1 to PCIe Gen2 in the 2007 time frame, PCIe Gen2 is now becoming widely adopted in the embedded, communications, and CPE markets. PCIe Gen2 ports are now commonly found in general-purpose microprocessors, FPGAs, SoCs, and ASICs.As higher resolution digital media is being created, stored, streamed,and displayed, consumer electronics devices are also adopting PCIe.Today’s high-end digital televisions, DSLR cameras and home gateways areall taking advantage of the high data rate capabilities that the PCIeinterconnect has to offer.

Jitter performance
As thedata rates and bandwidths have scaled upwards, so have the performancerequirements of reference clocks. Table 1 provides a snapshot of themaximum jitter requirements corresponding to each of the three PCIegeneration specifications.

Table 1: PCIe Clocking Architectures

Systemdesigners should consider their total clock jitter budget and not justthe jitter of a single clock generator or buffer. Ideally, designersshould specify clock generators and buffers that offer jitterperformance well within the maximum specifications set by the PCI-SIG.Optimal PCIe timing solutions should offer more than a 50 percentmargin.

Power consumption
Energy consumption andassociated costs have become a paramount issue for data center operatorsand owners. Data centers are large consumers of servers and storagesystems. Most PCIe clock generator and buffer solutions in the marketuse constant current mode, HCSL output buffer technology, firstdeveloped in the early 2000s for the PC market. As the name suggests,each output consumes a constant current, so clock outputs arecontinuously burning power. Optimal clock generator and buffer solutionsuse low-power push-pull output buffer technology, which converselyprovides a constant voltage source. These output buffers provide anoutput signal fully compatible to HCSL for PCIe applications, with theadded benefit of a 66 percent power consumption reduction over theconstant current mode solutions.

Edge rate / skew tuning
Best-in-classclock generators and buffers optimized for PCIe applications featureI2C programmable edge rate and skew features. With these PCIe timingdevices, each output can be individually tuned to the PCB environment,reducing electromagnetic interference (EMI). Mismatch in the edge rateand skew will create common mode energy that radiates EMI as well as anunstable cross point that causes data loss. Clock outputs commonly drivemultiple buses with the outputs. Therefore, any clock misalignmentswill add up to a large amount of common mode energy. Having thecapability to quickly tune the skew or edge rates of a particular outputcould potentially prevent board re-spins.

Board space and BOM
Boardspace and bill-of-materials (BOM) cost are always criticalconsiderations in consumer and embedded applications. In addition topower consumption savings, another advantage of using low-powerpush-pull output buffers is that all terminating resistors areintegrated. This saves up to four resistors per clock output, reducingBOM cost as well as total PCB area needed for the PCIe timing solution.Addressing these consumer electronics market needs, Silicon Labs’ offersthe SI52111-xx, Si52112-xx and Si53102 PCIe clock ICs insmall-form-factor 3 mm x 3 mm 10-pin TDFN and 1.4 mm x 1.6 mm 8-pin TDFNpackages.

PCIe has become the high-speedinterconnect of choice in the server/storage, embedded, communications,and consumer markets. Technology trends have contributed to theproliferation of PCIe from generation to generation, with theserver/storage markets adopting the newer standards first. As the datarate and bandwidth capabilities have scaled from Gen1 to Gen2 to Gen3,clock generator performance has become increasingly important as well.Jitter performance, power consumption, signal integrity, EMI, BOM cost,and total PCB area are also critical factors that designers must takeinto consideration.

Kyle Beckmeyer is productmarketing manager for Silicon Labs’ timing products,including those for awide array of clock generator and buffer solutions that meet the PCIeGen1.1, 2.1 and 3.0 specification. tojoiningSilicon Labs in 2013 he worked in the consumer and computingtiming divisions at Integrated Device Technology (IDT) as well asIntegrated Circuit Systems (ICS), focusing on timing products for theconsumer, computing, and embedded timing markets. Mr. Beckmeyer holds aBachelor of Science degree in electrical engineering from the Universityof California, Davis and a master’s degree in business administrationfrom Santa Clara University.

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