Using Continuous time DeltaSigma ADCs to reduce power consumption in high speed designs -

Using Continuous time DeltaSigma ADCs to reduce power consumption in high speed designs


Continuous timeDelta-Sigma ADC technology shatters the conventional wisdom thatpipeline ADCs are the only conversion technique available forhigh-speed, dynamic range applications. CT Delta Sigma technologyoffers lower-power operation, better dynamic performance and economy ofdesign.

Continuous time Delta Sigma is an inherently power-efficientarchitecture that eliminates power-hungry sample-and-hold  amplifiers (SHA) and the wide-bandwidth gain stages essential to the pipeline ADC concept. Analias-free Nyquist sample range is madeavailable by exploiting inherent oversampling and on-chip digitalfiltering.

Digital filtering permitstailoring of group delay performance and the signal transfer functionto specific applications. The integration of a clock and low jitterPLL, elimination of anti-aliasing filters andintegration of input gain stages simplify input signal path design ofhigh-resolution data-conversion systems. Switchless designfuture-proofs continuous delta sigma technology through its easymigration to next-generation CMOS processes, enabling greater speed andpower benefits.

The architecture supports high-resolution ADC systems from 10 bit to16 bit and beyond with sampling rates up to 100MHz. Today, most ADCdesigns aim to reduce power, particularly in high-speed conversion, andto minimize the number of comparators needed.

Pros and cons
It is broadly assumed that the pipeline converter provides the highestsample rates while yielding a high dynamic range. It is used as astandard in data-conversion applications at 10 bit and higherresolutions, and for sample rates from 5MHz to 100MHz or more. Thearchitecture reduces the number of comparators needed by deployingmultiple low-resolution flash conversion stages cascaded together toform the pipe.

Although the resolution of each conversion stage is reduced, thefirst stage must be designed with linearity at least as good as themaximum resolution of the ADC (12bit linearity for a 12bit ADC).Different pipeline implementations exist, but all work by reducing amultibit conversion into several lower-resolution “flashes” that areprocessed synchronously. At each stage in the pipe, a reconstruction ofthe previous stage's quantized output generated by a DAC is subtracted from theoriginal input signal.

The residual signal is then amplified before moving onto the nextstage for finer quantization. In pipeline conversion, a SHA needs toacquire the input signal and hold it to better than 0.5 LSB for the conversion'sduration. Once all sub-stages have a valid conversion result, a digitalcorrection block constructs the final multibit result.

The pipeline ADC is capable of high dynamic performance. However,beyond 12bit resolution and as the sampled signal moves through thepipeline, transferring the charge associated with a given signaldemands high-gain bandwidth to ensure that stage settling times fallwithin the limits set by the high-frequency signals being sampled.

To maintain linearity, you need to calibrate and correct for thelimits in component matching achievable with current processtechnologies; it is tough to migrate designs from one process toanother. As operating voltages fall from one process generation to thenext, the input signal headroom is compressed. Furthermore, designingswitches with reduced threshold voltages that work well indeep-submicron processes gets harder.

Remember that pipeline ADCs form only part of a data-conversionsystem – in addition, you need to find a low-jitter clock source anddesign input stages that include anti-alias filters (AAFs). In AAFdesign, steep attenuation characteristics are hard to achieve, temptingyou to consider over-sampling the signal of interest. Over-samplingstretches the Nyquist zone, lowering demands on filter roll-off.

Looking at the trade offs
But the trade-offs are increased system power and higher processingspeeds demanded of the back-end DSP system. With CT Delta-Sigmaconversion, on the other hand, you don't need an AAF. The Delta-Sigmaconverter uses a low-resolution quantizer – often only 1bit – clocked at rates considerably greater than Nyquist demands. The quantizercreates many low-resolution samples that – averaged over time – yieldan increased dynamic range.

The analog design is potentially straightforward, given thelinearity of a 1bit (2-level) quantizer. In the digital domain,filtering and decimation – the process of sample-rate reduction – areneeded to reconstruct output data and remove out-of-band noise. Figure 1 below shows the simplestsingle-order DS modulator block. It comprises a summing node,integrator and comparator.

Figure1: The simplest single-order Delta Sigma modulator block components areclocked at oversampling frequency.

The comparator's output feeds a 1bit DAC that closes the modulator'sfeedback loop. The modulator compares the input signal against avoltage reference level fed back from the DAC. The comparator isclocked at the oversampling frequency. Assuming enough loop gain, themodulator is a pulse stream, the density of 1s or 0s of which is adirect digital representation of the input signal. The DAC switchesbetween Vref to close the control loop.

For the Delta Sigma ADC, resolution increases are gained bybalancing the over-sampling ratio, Delta Sigma modulator order andquantizer resolution. Oversampling allows sample frequency/SNR trade-off and improvesdynamic range. It gives a 6dB (or 1bit's worth) SNR improvement forevery quadrupling of the sample rate, but dynamic range is moreeffectively enhanced by increasing the resolution of the quantizerand/or by adding more integration stages to the modulator.

Noise shaping is a property of Delta Sigma ADCs resulting from theapplication of feedback that extends dynamic range. This feature isbest illustrated by the mathematical analysis of the feedback controlloop of the Delta Sigma modulator as modeled in the frequency domain (Figure 2, below ).

Figure2: The quantization error is modeled as Q added to the modulator output.

This model reveals the key value of the Delta Sigma modulator. A closed loopmodulator works as a high-pass filter to quantization noise and as alow-pass filter to the input signal. The effect of this is a furtherincrease in dynamic range of 9dB for each doubling of the sample rate.Additional integrators within the loop can increase the steepness ofthe noise characteristic, giving further dynamic range increases.

Figure 3 below showssimulation results for the noise power density for the Delta Sigmamodulator used in a CT Delta Sigma ADC. This FFTplot (with 65k points) of the modulator illustrates the noise powerdensity (per FFT bin) relative to the input signal frequency. Thesimulation was driven with an input signal frequency of approximately4.8MHz.

Figure3: The quantization noise simulation result hints at the unrealizeddynamic range of a multibit Delta Sigma modulator used in a CT DeltaSigma ADC.

The minimum noise power density achieved by this modulator is166dBc/Hz (in the pass band). Note the characteristic of theout-of-band noise – i.e. those frequencies above 20MHz. Here, noisepower levels rise at the rate of 21dB/octave, a telltale sign of athird order modulator.

Deployed within this ADC design is a 16-level (or 4bit) quantizerthat delivers 14bit dynamic range at modest over sampling rates. Havingestablished a modulator system capable of achieving these low noiselevels, the next stage is to apply filtering to eliminate out-of-bandnoise and decimation to resample the data.

A digital filter must reject all signal components within the serialdata stream that occurs beyond the Nyquist bandwidth. Simplistically,two frequency-selective filter structures can be implemented in thedigital domain. They are the finite and infinite impulse responsefilter systems (FIRs and IIRs , respectively). FIRs aremore widely used because they are simpler and have a linear phaseresponse. IIR filter design is more complicated by virtue of thefeedback included.

The potentially infinite response of the IIR filter means that thereis always a possibility for the filter to become unstable. In addition,group delay can become significant and have adverse effects onperformance in some systems. Many degrees of freedom exist for signaltransfer function optimization in a CT Delta-Sigma ADC by combiningdifferent filter algorithms. However, optimal solutions may requiremany cascaded stages of FIR and IIR sections. Digital filtering allowsfor the data reduction or downsampling necessary to provide output dataat the originally intended sample rate.

In summary, the basic elements of a Delta-Sigma ADC areover-sampling, noise shaping and digital filtering. Oversamplingspreads quantization noise; noise shaping reduces the in-band noise atthe expense of higher out-of-band noise; and digital filteringattenuates out-of-band noise and signal components.

CT vs. discrete time systems
Most Delta-Sigma converters found in audio and precision applicationsexploit switched capacitor, discrete time (DT), loop filters within themodulator for noise shaping. Switched capacitor filters create theirown mixing products, and the DT Delta Sigma design is susceptible tothis type of noise aliasing. But the advantage of DT schemes is theirrelatively simple architecture – the way that increased sample ratesproduce dynamic range improvements and their compatibility with VLSICMOS processes.

However, the switched capacitor stages act as a limit on the maximumsignal bandwidth in the DT Delta-Sigma ADC. Moving to CT loop filtersopens up new application possibilities including wide baseband samplingout to several tens of MHz to under-sampling RF signals in bandpassdesigns. Pipeline and DT Delta-Sigma ADCs have a common design thread.In discrete time, sampling an input signal requires the signal to beacquired at a precise moment.

For an accurate representation of the input signal, the input stagesshould settle to a finite level, dictated by the accuracy limits of thesystem and a time period driven by the system sample-rate needs. Thissettling time eats into the sample time period of the system.

At 40 MSps, a conversion system can have a sample period of just25ns, setting the maximum time limits for circuit settling. At higherresolutions, this drives the need for very high gain bandwidth circuitswithin the acquisition signal path. In fact, the converter system mustbe designed with circuits that work with bandwidths many times that ofthe input signal.

Thus, discrete time circuits have to burn excess power to process agiven bandwidth. The move to a CT strategy eliminates the settling timeissue altogether, allowing either a lower-power CT Delta-Sigma ADCimplementation vs. discrete time, at a given sample rate or a highersample rate for a given power budget. There is no acquisition phase inCT Delta-Sigma , so a high performance sample-and-hold stage iseliminated. CT does not require the high-gain bandwidth stagesnecessary to force rapid settling, so power in these stages is reduced.

A little more power is demanded from the post modulator digitalfilter stages, but the CT loop filter reduces the power demands of themodulator and eliminates the additional discrete time-sampling effectsseen in the DT DS ADC. In addition, there is no down-mixing of noise,eliminating any additional spectral spurs in the baseband.

With CT Delta-Sigma the filter performance is dependent onconventional active filter design rules. If the sample rate is changedto match input signal bandwidth, the CT filter must be tuned. Thus, apotential limit on the CT Delta-Sigma implementation is how to ensurethat a wide range of sample rates can be supported from a singleproduct platform. This problem is solved using adaptive filter combinedwith calibration techniques.

For high-resolution implementations, the loop filter must havesignificant gain to obtain high linearity. This is provided usingmultipath and cascaded gain stages operating at 1.2V and delivering80dB of gain for a 30MHz bandwidth. This has been clearly demonstratedas possible in 0.1µm CMOS. The first product to implement CTDelta-Sigma conversion offers a low-power alternative to the pipelineconverter. It is said to be a complete data-conversion system, designedto operate seamlessly over a wide range of sample rates withouthigh-performance, expensive and external components.

Simplify application
Xignal's implementation of a CT Delta-Sigma quantizer and digitalfiltering supports resolutions up to and beyond 14bits. Thegeneral-purpose ADC core is combined with several features designed tosimplify its application. It consumes less power – 60mW for the ADCcore, leading to an energy figure of merit(FOM) of 0.79pJ/conversion.

The CTDS ADC architecture eliminates complex input filtering due tothe effect of oversampling in combination with digital filtering (Figure 4, below ). With filterperformance characteristics set in the digital domain, a very highlevel of pass-band flatness and steep roll-off is possible. The currentdigital filter allows 90 percent of the first Nyquist zone to beexploited whilst offering a pass-band ripple of only ±0.0002dBand 80dB stop-band attenuation. Group delay for this filter is only0.33 samples.

Figure4: CT Delta Sigma ADC eliminates complex input filtering.

A third-order CTDS modulator is used, designed around a 4bitquantizer stage achieving dynamic range at an oversampling rate of 16.The differential input signal path has a bandwidth of 30MHz. Theinternal sample clock operates at 640MHz. Today's technol¬ogyallows for increased sample rates to 80MSps (at 14bits) with anover-sampling clock rate of approximately 1.3GHz. Through self-adaptivetunable loop filter components, the ADC is optimized for sample ratesof 20MSps to 40MSps.

The clock source is integrated on-chip with the ADC core. The ADCjust needs a low-cost crystal, parallel connected to its clock input.The clock is connected to a high-performance PLL block that uses an on-chipLC-tuned circuit to create a high-Qresonator , creating a precise clock source.

Alternatively, an external clock can drive the ADC. High-frequencyjitter from an external distributed clock tree will be removed,provided its jitter falls outside the 350kHz PLL bandwidth of thejitter cleaner circuit. However, an advantage of the on-chip precisionclock is that it can be routed to external circuits. Furthermore, itcan be used as a system reference clock for other time-critical partsof the system, potentially eliminating the extra cost of a low-jittersource, saving both design effort and board area.

A low-jitter clock is a crucial function in all high-speed,high-resolution data-conversion systems. Phase accuracy of the sampleclock has a major impact on measured performance. In fact, decibels ofdynamic range are easily sacrificed by picoseconds of phase jitter.

Figure 5 below shows themathematical derivation of maximal clock jitter for a given resolutionand input signal frequency. For a 10MHz bandwidth signal, at 12bitresolution, clock jitter must be less than 3ps rms. For 14bits, thisdemand drops to 1ps rms.

Figure5: For a 10MHz bandwidth signal, at 12bit resolution, clock jitter mustbe less than 3ps rms.

The initial results are encouraging and better than the FOMsachieved by contemporary pipeline ADC designs. Furthermore, thearchitecture has the ability to scale with CMOS process developmentsand to yield further increases in efficiency and speed. This isimportant as pipeline design will become more challenging within therestrictive confines of the CMOS process roadmap with its sub-bandgapthreshold requirements.

The ongoing development at Xignal shows that the ADC core can besuccessfully combined with input signal path components to provide ahigh level of integration. The digital processing (filtering anddecimation) provided also shows that in the future, it is possible forsystem designers to tailor-transfer functions for a given application.Finally, the elimination of external anti-alias networks and theinclusion of a high-performance PLL significantly ease the design of ahigh-resolution, high-speed sampling system.

The quantization noise simulation result hints at the unrealizeddynamic range of a multibit DS modulator. There is some room forfurther dynamic range improvements with careful design, particularlywith thermal noise – the dominant noise source in this design today.Although complex, the deployed CTDS ADC has been implemented in such away to be transparent to the user.

Mark Holdaway is director ofProduct Marketing, ADC Products, at XignalTechnologies GmbH,  now a  subsidiary of National Semiconductor.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.