Using correct-by-construction techniques and tools to simplify board design -

Using correct-by-construction techniques and tools to simplify board design


Each new generation of silicon – such as 90nm and 45nm – brings a setof end-user benefits such as lower cost, lower power and newfunctionality.

It also brings new printed circuitboard (PCB) design-in challenges including smaller footprints,simultaneous switching noise and faster edge rates (Figure 1 below ). These challengestranslate into a set of new constraints for designing a PCB.

Figure1: Each new generation of silicon brings a set of end-user benefits aswell as new PCB design challenges.

Over the past decade, the number of nets on a PCB that haveconstraints has gone up significantly, sometimes approaching 100percent of nets on a PCB. New I/O interfaces such as DDR2, DDR3 and PCIemake it easier to design aPCB.

However, these I/O interfaces also add constraints on how theyshould be designed at the physical level. Increasing number ofconstraints, if not handled properly, can extend the PCB design cycleand, worse, require physical prototype iterations that also addmaterial costs.

PCB designers need a methodology that can help them avoid designiterations between the design and layout stages, or finding issues withthe board in the lab with a physical prototype. This article discusseshow a “correct- by-construction” PCB layout methodology can help PCBdesigners shorten their design cycle.

Smart technique
Enabling a correct-by-construction approach requires two fundamentalthings – first is a way to specify complete design intent (not justconnectivity) and second, a methodology that ensures the design intentis met throughout the design process.

Specifying complete design intent requires that engineers should beable to marry constraints with the traditional connectivity data. Insome cases, the design intent can be refined as the design progressesfrom logical to physical design. Since many, if not most, designs reusesections from previous designs, the benefits of creating completedesign intent can be reaped in subsequent designs.

Once the design intent is specified and is part of the PCB,designers need a methodology that can provide feedback at every step ofthe design process. This feedback helps avoid design iterations,shortening the design cycle. This, together with post-layoutverification using simulation, helps ensure that designers avoid costlyand time-consuming physical prototype iterations.

Connectivity – which components to use on the board and how they areconnected – has been part of EDA for PCB design since early 1980s.Marrying constraints to the connectivity is required to complete thedesign intent.

Constraints can be categorized in five groups: physical, spacing,electrical, thermal and mechanical. Physical and spacing constraints inthe past used to be driven by manufacturing processes.

Today, they are influenced by manufacturing and electricalrequirements. Electrical constraints on nets have been growing rapidly.The number of nets that have constraints on the board and the number ofconstraints on a net have both increased.

This explosion of constraints on the board requires a methodologyfor designing the physical layout of the board that provides feedbackas the design progresses. Designers need a way to get real-timefeedback as placement is done.

During placement, the EDA environment must provide feedback toensure that electrical, mechanical or thermal constraints are not beingviolated. Many users don't have mechanical or thermal constraints ontheir board but today, it's hard to find PCBs without electricalconstraints on any of the nets on the board. With advanced I/Ointerfaces for memories like DDR2 and DDR3, all market segments willhave to deal with constraints for designing PCBs.

Without real-time feedback as the design progresses from placementto routing to etch editing, users will discover issues too late in thedesign cycle – either during post-layout simulation or during thephysical prototype debug in the lab. Discovering these issues after thelayout is complete can add time-consuming design iterations.

Assuming you have an environment that enables acorrect-by-construction or a constraint-driven PCB design approach,designers must develop constraints for signals or nets on the PCB andembed them with the connectivity specification. Constraints originatefrom different domains: manufacturing, electrical, thermal andmechanical.

Info from vendors
In some segments, IC vendors provide a detailed design-in methodologyand electrical constraints for signals on new, complex devices. Thismakes designing-in these complex devices quick and easy. In othercases, PCB designers or SI engineers have to develop constraints usingsimulation.

Figure2: With 50-75 percent of nets constrained on a dense, complex board,convergence is not guaranteed.

Several years ago, many designers resorted to post-layout simulationto identify and fix problems in the design before manufacturing theboard. This approach was acceptable when there were few high-speed netson the PCB.

As the number of high-speed nets on the PCB grew, timing marginsshrank and the supply voltage went down to satisfy low power needs forelectronic devices. It became very difficult to ensure that post-layoutsimulation-debug-fix cycle would converge.

The design cycle was not predictable if simulation was first doneafter layout was completed (Figure 2above ). Over time, the simulation and constraint generationmoved earlier in the design cycle – from post-layout to post-placementto pre-placement and for some new and advanced interfaces, topreschematic.

<>Doing simulation to develop constraints earlier in the cycleallowsdesigners to integrate constraints with the connectivity definition. Toshorten the constraint development cycle, PCB designers can ask fordesign-in help from the chipmaker, especially for devices that useadvanced I/O interfaces like PCIe Gen2, Serial ATA II, DDR2 and DDR3.

Most companies that develop ICs with such advanced I/O interfaces dosimulation internally to develop datasheet for their devices. Many ICvendors also develop and provide reference designs to their customersto show that their device works on a PCB and to give their customers astarting point to design-in the device.

This means that some of the work to evaluate the new device isalready done and provided to PCB designers in electronic form, like anelectronic, executable datasheet. Once the device is chosen, the workdone to evaluate the device and the reference design can be reused forfinal PCB design.

This gets even better if the chipmaker also uses a correct-by-construction approach and has a way to integrate constraints withconnectivity for their reference board. With this setup, PCB designerscan shorten their time to design-in new and advanced ICs. This is alsobeneficial for IC companies since shorter design-in cycle for theirchips results in faster time-to-volume production.

Another resource for designing- in devices with advanced I/Ointerfaces is the design-in IP portfolios of EDA companies, often donein collaboration with multiple IC vendors. The design-in IP portfolioscan include ready to simulate single- or multiple-board topologies tohelp evaluate the device to constraints embedded in schematics andphysical database of the reference design to reuse subsets ofschematics and board design, shortening overall design-in time.

With increasing number of nets on the board and increasing number ofconstraints on nets, it is important to develop constraints early inthe design cycle, integrate them with connectivity to provide the mostpossible complete design intent.

Using a correct-by-construction or constraint-driven PCB design flowthat provides feedback on deviation from design intent at every step ofthe way will reduce or eliminate design iterations, shorten designcycle and reduce if not eliminate physical prototype iterations.

Ask your IC supplier for executable, reusable design-in datasheetspreferably with a reference design that has design intent specified andconstraints embedded in the physical design. Look for design-in IPportfolios that may be provided by EDA vendors collaborating with ICcompanies for advanced I/O interfaces like DDR2 and PCIe.

Hemant Shah is Marketing Directorof the High Speed Systems Design Group at Cadence Design Systems.

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